NXP Semiconductors
LPC812M101JTB16
2024.06.02
LPC812M101JTB16
Cortex-M0
r1p0
little
3
false
ACOMP
analog comparator
ACOMP
0x0
0x0
0x8
registers
n
CTRL
Comparator control register
0x0
32
read-write
n
0x0
0x0
COMPEDGE
Comparator edge-detect status.
23
1
read-write
COMPSA
Comparator output control
6
1
read-write
COMPSA_0
Comparator output is used directly.
0
COMPSA_1
Comparator output is synchronized to the bus clock for output to other modules.
0x1
COMPSTAT
Comparator status. This bit reflects the state of the comparator output.
21
1
read-write
COMP_VM_SEL
Selects negative voltage input
11
3
read-write
VOLTAGE_LADDER_OUTPUT
VOLTAGE_LADDER_OUTPUT
0
ACMP_I1
ACMP_I1
0x1
ACMP_I2
ACMP_I2
0x2
ACMP_I3
ACMP_I3
0x3
ACMP_I4
ACMP_I4
0x4
ACMP_I5
ACMP_I5
0x5
BAND_GAP
Band gap. Internal reference voltage.
0x6
DACOUT0
DAC0 output
0x7
COMP_VP_SEL
Selects positive voltage input
8
3
read-write
VOLTAGE_LADDER_OUTPUT
VOLTAGE_LADDER_OUTPUT
0
ACMP_I1
ACMP_I1
0x1
ACMP_I2
ACMP_I2
0x2
ACMP_I3
ACMP_I3
0x3
ACMP_I4
ACMP_I4
0x4
ACMP_I5
ACMP_I5
0x5
BAND_GAP
Band gap. Internal reference voltage.
0x6
DACOUT0
DAC0 output
0x7
EDGECLR
Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0.
20
1
read-write
EDGESEL
This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):
3
2
read-write
FALLING_EDGES
Falling edges
0
RISING_EDGES
Rising edges
0x1
BOTH_EDGES0
Both edges
0x2
BOTH_EDGES1
Both edges
0x3
HYS
Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.
25
2
read-write
HYS_0
None (the output will switch as the voltages cross)
0
HYS_1
5 mv
0x1
HYS_2
10 mv
0x2
HYS_3
20 mv
0x3
LAD
Voltage ladder register
0x4
32
read-write
n
0x0
0x0
LADEN
Voltage ladder enable
0
1
read-write
LADREF
Selects the reference voltage Vref for the voltage ladder.
6
1
read-write
LADREF_0
Supply pin VDD
0
LADREF_1
VDDCMP pin
0x1
LADSEL
Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref
1
5
read-write
CRC
LPC5411x CRC engine
CRC
0x0
0x0
0xC
registers
n
MODE
CRC mode register
0x0
32
read-write
n
0x0
0x0
BIT_RVS_SUM
CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
4
1
read-write
BIT_RVS_WR
Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
2
1
read-write
CMPL_SUM
CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
5
1
read-write
CMPL_WR
Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
3
1
read-write
CRC_POLY
CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
0
2
read-write
SEED
CRC seed register
0x4
32
read-write
n
0x0
0x0
CRC_SEED
A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses.
0
32
read-write
SUM
CRC checksum register
SUM_WR_DATA
0x8
32
read-only
n
0x0
0x0
CRC_SUM
The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
0
32
read-only
WR_DATA
CRC data register
SUM_WR_DATA
0x8
32
write-only
n
0x0
0x0
CRC_WR_DATA
Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.
0
32
write-only
FLASH_CTRL
NVMC flash controller
FLASH_CTRL
0x0
0x0
0x30
registers
n
FLASHCFG
Flash configuration register
0x10
32
read-write
n
0x0
0x0
FLASHTIM
Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
0
2
read-write
ONE_SYSTEM_CLOCK_FLASH_ACCESS
1 system clock flash access time.
0
TWO_SYSTEM_CLOCK_FLASH_ACCESS
2 system clock flash access time.
0x1
THREE_SYSTEM_CLOCK_FLASH_ACCESS
3 system clock flash access time.
0x2
FMSSTART
Flash signature start address register
0x20
32
read-write
n
0x0
0x0
START
Signature generation start address (corresponds to AHB byte address bits[18:2]).
0
17
read-write
FMSSTOP
Flash signaure stop address register
0x24
32
read-write
n
0x0
0x0
STOPA
Stop address for signature generation (the word specified by STOP is included in the address range). The address is in units of memory words, not bytes.
0
17
read-write
STRTBIST
When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared.
31
1
read-write
FMSW0
Flash signature generation result register returns the flash signature produced by the embedded signature generator..
0x2C
32
read-only
n
0x0
0x0
SIG
32-bit signature.
0
32
read-only
GPIO
General Purpose I/O (GPIO)
GPIO
0x0
0x0
0x2304
registers
n
B0_0
Byte pin registers for all port 0 and 1 GPIO pins
0x0
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_1
Byte pin registers for all port 0 and 1 GPIO pins
0x1
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_10
Byte pin registers for all port 0 and 1 GPIO pins
0xA
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_11
Byte pin registers for all port 0 and 1 GPIO pins
0xB
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_12
Byte pin registers for all port 0 and 1 GPIO pins
0xC
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_13
Byte pin registers for all port 0 and 1 GPIO pins
0xD
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_14
Byte pin registers for all port 0 and 1 GPIO pins
0xE
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_15
Byte pin registers for all port 0 and 1 GPIO pins
0xF
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_16
Byte pin registers for all port 0 and 1 GPIO pins
0x10
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_17
Byte pin registers for all port 0 and 1 GPIO pins
0x11
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_2
Byte pin registers for all port 0 and 1 GPIO pins
0x2
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_3
Byte pin registers for all port 0 and 1 GPIO pins
0x3
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_4
Byte pin registers for all port 0 and 1 GPIO pins
0x4
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_5
Byte pin registers for all port 0 and 1 GPIO pins
0x5
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_6
Byte pin registers for all port 0 and 1 GPIO pins
0x6
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_7
Byte pin registers for all port 0 and 1 GPIO pins
0x7
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_8
Byte pin registers for all port 0 and 1 GPIO pins
0x8
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
B0_9
Byte pin registers for all port 0 and 1 GPIO pins
0x9
8
read-write
n
0x0
0x0
PBYTE
Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
1
read-write
CLR0
Clear port
0x2280
32
write-only
n
0x0
0x0
CLRP
Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit.
0
18
write-only
DIR0
Direction registers
0x2000
32
read-write
n
0x0
0x0
DIRP
Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output.
0
18
read-write
MASK0
Mask register
0x2080
32
read-write
n
0x0
0x0
MASKP
Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected.
0
18
read-write
MPIN0
Masked port register
0x2180
32
read-write
n
0x0
0x0
MPORTP
Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0.
0
18
read-write
NOT0
Toggle port
0x2300
32
write-only
n
0x0
0x0
NOTP
Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit.
0
18
write-only
PIN0
Port pin register
0x2100
32
read-write
n
0x0
0x0
PORT
Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit.
0
18
read-write
SET0
Write: Set register for port Read: output bits for port
0x2200
32
read-write
n
0x0
0x0
SETP
Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit.
0
18
read-write
W0_0
Word pin registers for all port 0 and 1 GPIO pins
0x1000
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_1
Word pin registers for all port 0 and 1 GPIO pins
0x1004
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_10
Word pin registers for all port 0 and 1 GPIO pins
0x1028
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_11
Word pin registers for all port 0 and 1 GPIO pins
0x102C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_12
Word pin registers for all port 0 and 1 GPIO pins
0x1030
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_13
Word pin registers for all port 0 and 1 GPIO pins
0x1034
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_14
Word pin registers for all port 0 and 1 GPIO pins
0x1038
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_15
Word pin registers for all port 0 and 1 GPIO pins
0x103C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_16
Word pin registers for all port 0 and 1 GPIO pins
0x1040
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_17
Word pin registers for all port 0 and 1 GPIO pins
0x1044
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_2
Word pin registers for all port 0 and 1 GPIO pins
0x1008
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_3
Word pin registers for all port 0 and 1 GPIO pins
0x100C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_4
Word pin registers for all port 0 and 1 GPIO pins
0x1010
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_5
Word pin registers for all port 0 and 1 GPIO pins
0x1014
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_6
Word pin registers for all port 0 and 1 GPIO pins
0x1018
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_7
Word pin registers for all port 0 and 1 GPIO pins
0x101C
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_8
Word pin registers for all port 0 and 1 GPIO pins
0x1020
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
W0_9
Word pin registers for all port 0 and 1 GPIO pins
0x1024
32
read-write
n
0x0
0x0
PWORD
Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package.
0
32
read-write
I2C0
I2C-bus interfaces
I2C
0x0
0x0
0x84
registers
n
I2C0
8
CFG
Configuration for shared functions.
0x0
32
read-write
n
0x0
0x0
MONCLKSTR
Monitor function Clock Stretching.
4
1
read-write
DISABLED
Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.
0
ENABLED
Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.
0x1
MONEN
Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.
2
1
read-write
DISABLED
Disabled. The I2C Monitor function is disabled.
0
ENABLED
Enabled. The I2C Monitor function is enabled.
0x1
MSTEN
Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.
0
1
read-write
DISABLED
Disabled. The I2C Master function is disabled.
0
ENABLED
Enabled. The I2C Master function is enabled.
0x1
SLVEN
Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.
1
1
read-write
DISABLED
Disabled. The I2C slave function is disabled.
0
ENABLED
Enabled. The I2C slave function is enabled.
0x1
TIMEOUTEN
I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
3
1
read-write
DISABLED
Disabled. Time-out function is disabled.
0
ENABLED
Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.
0x1
CLKDIV
Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.
0x14
32
read-write
n
0x0
0x0
DIVVAL
This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is divided by 65,536 before use.
0
16
read-write
INTENCLR
Interrupt Enable Clear register.
0xC
32
write-only
n
0x0
0x0
EVENTTIMEOUTCLR
Event time-out interrupt clear.
24
1
write-only
MONIDLECLR
Monitor Idle interrupt clear.
19
1
write-only
MONOVCLR
Monitor Overrun interrupt clear.
17
1
write-only
MONRDYCLR
Monitor data Ready interrupt clear.
16
1
write-only
MSTARBLOSSCLR
Master Arbitration Loss interrupt clear.
4
1
write-only
MSTPENDINGCLR
Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented.
0
1
write-only
MSTSTSTPERRCLR
Master Start/Stop Error interrupt clear.
6
1
write-only
SCLTIMEOUTCLR
SCL time-out interrupt clear.
25
1
write-only
SLVDESELCLR
Slave Deselect interrupt clear.
15
1
write-only
SLVNOTSTRCLR
Slave Not Stretching interrupt clear.
11
1
write-only
SLVPENDINGCLR
Slave Pending interrupt clear.
8
1
write-only
INTENSET
Interrupt Enable Set and read register.
0x8
32
read-write
n
0x0
0x0
EVENTTIMEOUTEN
Event time-out interrupt Enable.
24
1
read-write
DISABLED
Disabled. The Event time-out interrupt is disabled.
0
ENABLED
Enabled. The Event time-out interrupt is enabled.
0x1
MONIDLEEN
Monitor Idle interrupt Enable.
19
1
read-write
DISABLED
Disabled. The MonIdle interrupt is disabled.
0
ENABLED
Enabled. The MonIdle interrupt is enabled.
0x1
MONOVEN
Monitor Overrun interrupt Enable.
17
1
read-write
DISABLED
Disabled. The MonOv interrupt is disabled.
0
ENABLED
Enabled. The MonOv interrupt is enabled.
0x1
MONRDYEN
Monitor data Ready interrupt Enable.
16
1
read-write
DISABLED
Disabled. The MonRdy interrupt is disabled.
0
ENABLED
Enabled. The MonRdy interrupt is enabled.
0x1
MSTARBLOSSEN
Master Arbitration Loss interrupt Enable.
4
1
read-write
DISABLED
Disabled. The MstArbLoss interrupt is disabled.
0
ENABLED
Enabled. The MstArbLoss interrupt is enabled.
0x1
MSTPENDINGEN
Master Pending interrupt Enable.
0
1
read-write
DISABLED
Disabled. The MstPending interrupt is disabled.
0
ENABLED
Enabled. The MstPending interrupt is enabled.
0x1
MSTSTSTPERREN
Master Start/Stop Error interrupt Enable.
6
1
read-write
DISABLED
Disabled. The MstStStpErr interrupt is disabled.
0
ENABLED
Enabled. The MstStStpErr interrupt is enabled.
0x1
SCLTIMEOUTEN
SCL time-out interrupt Enable.
25
1
read-write
DISABLED
Disabled. The SCL time-out interrupt is disabled.
0
ENABLED
Enabled. The SCL time-out interrupt is enabled.
0x1
SLVDESELEN
Slave Deselect interrupt Enable.
15
1
read-write
DISABLED
Disabled. The SlvDeSel interrupt is disabled.
0
ENABLED
Enabled. The SlvDeSel interrupt is enabled.
0x1
SLVNOTSTREN
Slave Not Stretching interrupt Enable.
11
1
read-write
DISABLED
Disabled. The SlvNotStr interrupt is disabled.
0
ENABLED
Enabled. The SlvNotStr interrupt is enabled.
0x1
SLVPENDINGEN
Slave Pending interrupt Enable.
8
1
read-write
DISABLED
Disabled. The SlvPending interrupt is disabled.
0
ENABLED
Enabled. The SlvPending interrupt is enabled.
0x1
INTSTAT
Interrupt Status register for Master, Slave, and Monitor functions.
0x18
32
read-only
n
0x0
0x0
EVENTTIMEOUT
Event time-out Interrupt flag.
24
1
read-only
MONIDLE
Monitor Idle flag.
19
1
read-only
MONOV
Monitor Overflow flag.
17
1
read-only
MONRDY
Monitor Ready.
16
1
read-only
MSTARBLOSS
Master Arbitration Loss flag.
4
1
read-only
MSTPENDING
Master Pending.
0
1
read-only
MSTSTSTPERR
Master Start/Stop Error flag.
6
1
read-only
SCLTIMEOUT
SCL time-out Interrupt flag.
25
1
read-only
SLVDESEL
Slave Deselected flag.
15
1
read-only
SLVNOTSTR
Slave Not Stretching status.
11
1
read-only
SLVPENDING
Slave Pending.
8
1
read-only
MONRXDAT
Monitor receiver data register.
0x80
32
read-only
n
0x0
0x0
MONNACK
Monitor Received NACK.
10
1
read-only
ACKNOWLEDGED
Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
0
NOT_ACKNOWLEDGED
Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
0x1
MONRESTART
Monitor Received Repeated Start.
9
1
read-only
NOT_DETECTED
No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
0
DETECTED
Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
0x1
MONRXDAT
Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
0
8
read-only
MONSTART
Monitor Received Start.
8
1
read-only
NO_START_DETECTED
No start detected. The Monitor function has not detected a Start event on the I2C bus.
0
START_DETECTED
Start detected. The Monitor function has detected a Start event on the I2C bus.
0x1
MSTCTL
Master control register.
0x20
32
read-write
n
0x0
0x0
MSTCONTINUE
Master Continue.
0
1
read-write
NO_EFFECT
No effect.
0
Continue
Informs the Master function to continue to the next operation.
0x1
MSTSTART
Master Start control.
1
1
read-write
NO_EFFECT
No effect.
0
START
Start. A Start will be generated on the I2C bus at the next allowed time.
0x1
MSTSTOP
Master Stop control.
2
1
read-write
NO_EFFECT
No effect.
0
STOP
Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).
0x1
MSTDAT
Combined Master receiver and transmitter data register.
0x28
32
read-write
n
0x0
0x0
DATA
Master function data register. Read: read the most recently received data for the Master function. Write: transmit data using the Master function.
0
8
read-write
MSTTIME
Master timing configuration.
0x24
32
read-write
n
0x0
0x0
MSTSCLHIGH
Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU STO and tHD STA have the same values and are also controlled by MSTSCLHIGH.
4
3
read-write
CLOCKS_2
2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
0
CLOCKS_3
3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
0x1
CLOCKS_4
4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
0x2
CLOCKS_5
5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
0x3
CLOCKS_6
6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
0x4
CLOCKS_7
7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
0x5
CLOCKS_8
8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
0x6
CLOCKS_9
9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
0x7
MSTSCLLOW
Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU STA have the same values and are also controlled by MSTSCLLOW.
0
3
read-write
CLOCKS_2
2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
0
CLOCKS_3
3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
0x1
CLOCKS_4
4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
0x2
CLOCKS_5
5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
0x3
CLOCKS_6
6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
0x4
CLOCKS_7
7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
0x5
CLOCKS_8
8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
0x6
CLOCKS_9
9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
0x7
SLVADR0
Slave address register.
0x48
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR1
Slave address register.
0x4C
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR2
Slave address register.
0x50
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR3
Slave address register.
0x54
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR[0]
Slave address register.
0x90
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR[1]
Slave address register.
0xDC
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR[2]
Slave address register.
0x12C
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVADR[3]
Slave address register.
0x180
32
read-write
n
0x0
0x0
SADISABLE
Slave Address n Disable.
0
1
read-write
ENABLED
Enabled. Slave Address n is enabled.
0
DISABLED
Ignored Slave Address n is ignored.
0x1
SLVADR
Slave Address. Seven bit slave address that is compared to received addresses if enabled.
1
7
read-write
SLVCTL
Slave control register.
0x40
32
read-write
n
0x0
0x0
SLVCONTINUE
Slave Continue.
0
1
read-write
NO_EFFECT
No effect.
0
Continue
Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
0x1
SLVNACK
Slave NACK.
1
1
read-write
NO_EFFECT
No effect.
0
NACK
NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
0x1
SLVDAT
Combined Slave receiver and transmitter data register.
0x44
32
read-write
n
0x0
0x0
DATA
Slave function data register. Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function.
0
8
read-write
SLVQUAL0
Slave Qualification for address 0.
0x58
32
read-write
n
0x0
0x0
QUALMODE0
Qualify mode for slave address 0.
0
1
read-write
MASK
Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
0
EXTEND
Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
0x1
SLVQUAL0
Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
1
7
read-write
STAT
Status register for Master, Slave, and Monitor functions.
0x4
32
read-write
n
0x0
0x0
EVENTTIMEOUT
Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.
24
1
read-write
NO_TIMEOUT
No time-out. I2C bus events have not caused a time-out.
0
EVEN_TIMEOUT
Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
0x1
MONACTIVE
Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.
18
1
read-only
INACTIVE
Inactive. The Monitor function considers the I2C bus to be inactive.
0
ACTIVE
Active. The Monitor function considers the I2C bus to be active.
0x1
MONIDLE
Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.
19
1
read-write
NOT_IDLE
Not idle. The I2C bus is not idle, or this flag has been cleared by software.
0
IDLE
Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
0x1
MONOV
Monitor Overflow flag.
17
1
read-write
NO_OVERRUN
No overrun. Monitor data has not overrun.
0
OVERRUN
Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
0x1
MONRDY
Monitor Ready. This flag is cleared when the MONRXDAT register is read.
16
1
read-only
NO_DATA
No data. The Monitor function does not currently have data available.
0
DATA_WAITING
Data waiting. The Monitor function has data waiting to be read.
0x1
MSTARBLOSS
Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
4
1
read-write
NO_LOSS
No Arbitration Loss has occurred.
0
ARBITRATION_LOSS
Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
0x1
MSTPENDING
Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.
0
1
read-only
IN_PROGRESS
In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
0
PENDING
Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.
0x1
MSTSTATE
Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.
1
3
read-only
IDLE
Idle. The Master function is available to be used for a new transaction.
0
RECEIVE_READY
Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
0x1
TRANSMIT_READY
Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
0x2
NACK_ADDRESS
NACK Address. Slave NACKed address.
0x3
NACK_DATA
NACK Data. Slave NACKed transmitted data.
0x4
MSTSTSTPERR
Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
6
1
read-write
NO_ERROR
No Start/Stop Error has occurred.
0
ERROR
The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.
0x1
SCLTIMEOUT
SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
25
1
read-write
NO_TIMEOUT
No time-out. SCL low time has not caused a time-out.
0
TIMEOUT
Time-out. SCL low time has caused a time-out.
0x1
SLVDESEL
Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.
15
1
read-write
NOT_DESELECTED
Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.
0
DESELECTED
Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
0x1
SLVIDX
Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.
12
2
read-only
ADDRESS0
Address 0. Slave address 0 was matched.
0
ADDRESS1
Address 1. Slave address 1 was matched.
0x1
ADDRESS2
Address 2. Slave address 2 was matched.
0x2
ADDRESS3
Address 3. Slave address 3 was matched.
0x3
SLVNOTSTR
Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.
11
1
read-only
STRETCHING
Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
0
NOT_STRETCHING
Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.
0x1
SLVPENDING
Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.
8
1
read-only
IN_PROGRESS
In progress. The Slave function does not currently need service.
0
PENDING
Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
0x1
SLVSEL
Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.
14
1
read-only
NOT_SELECTED
Not selected. The Slave function is not currently selected.
0
SELECTED
Selected. The Slave function is currently selected.
0x1
SLVSTATE
Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.
9
2
read-only
SLAVE_ADDRESS
Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
0
SLAVE_RECEIVE
Slave receive. Received data is available (Slave Receiver mode).
0x1
SLAVE_TRANSMIT
Slave transmit. Data can be transmitted (Slave Transmitter mode).
0x2
TIMEOUT
Time-out value register.
0x10
32
read-write
n
0x0
0x0
TO
Time-out time value. Specifies the time-out interval value in increments of 16 I 2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock.
4
12
read-write
TOMIN
Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
0
4
read-write
IOCON
I/O pin configuration (IOCON)
IOCON
0x0
0x0
0x4C
registers
n
PIO0
Digital I/O control for port 0 pins PIO0
0x0
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_0
Digital I/O control for pins PIO0_0
0x44
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_1
Digital I/O control for pins PIO0_1
0x2C
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_10
Digital I/O control for pins PIO0_10
0x20
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
I2CMODE
Selects I2C mode.
8
2
read-write
STANDARAD_I2C
Standard mode/ Fast-mode I2C.
0
Standard_GPIO
Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x1
FAST_PLUS_I2C
Fast-mode Plus I2C
0x2
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_11
Digital I/O control for pins PIO0_11
0x1C
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
I2CMODE
Selects I2C mode.
8
2
read-write
STANDARAD_I2C
Standard mode/ Fast-mode I2C.
0
Standard_GPIO
Standard GPIO functionality. Requires external pull-up for GPIO output function.
0x1
FAST_PLUS_I2C
Fast-mode Plus I2C
0x2
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_12
Digital I/O control for pins PIO0_12
0x8
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_13
Digital I/O control for pins PIO0_13
0x4
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_14
Digital I/O control for pins PIO0_14
0x48
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_15
Digital I/O control for pins PIO0_15
0x28
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_16
Digital I/O control for pins PIO0_16
0x24
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_17
Digital I/O control for pins PIO0_17
0x0
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_2
Digital I/O control for pins PIO0_2
0x18
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_3
Digital I/O control for pins PIO0_3
0x14
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_4
Digital I/O control for pins PIO0_4
0x10
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_5
Digital I/O control for pins PIO0_5
0xC
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_6
Digital I/O control for pins PIO0_6
0x40
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_7
Digital I/O control for pins PIO0_7
0x3C
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_8
Digital I/O control for pins PIO0_8
0x38
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO0_9
Digital I/O control for pins PIO0_9
0x34
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO1
Digital I/O control for port 0 pins PIO1
0x4
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO10
Digital I/O control for port 0 pins PIO10
0x28
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO11
Digital I/O control for port 0 pins PIO11
0x2C
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO12
Digital I/O control for port 0 pins PIO12
0x30
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO13
Digital I/O control for port 0 pins PIO13
0x34
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO14
Digital I/O control for port 0 pins PIO14
0x38
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO15
Digital I/O control for port 0 pins PIO15
0x3C
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO16
Digital I/O control for port 0 pins PIO16
0x40
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO17
Digital I/O control for port 0 pins PIO17
0x44
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO18
Digital I/O control for port 0 pins PIO18
0x48
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO2
Digital I/O control for port 0 pins PIO2
0x8
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO3
Digital I/O control for port 0 pins PIO3
0xC
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO4
Digital I/O control for port 0 pins PIO4
0x10
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO5
Digital I/O control for port 0 pins PIO5
0x14
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO6
Digital I/O control for port 0 pins PIO6
0x18
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO7
Digital I/O control for port 0 pins PIO7
0x1C
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO8
Digital I/O control for port 0 pins PIO8
0x20
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
PIO9
Digital I/O control for port 0 pins PIO9
0x24
32
read-write
n
0x0
0x0
CLK_DIV
Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
13
3
read-write
CLK_DIV_0
IOCONCLKDIV0
0
CLK_DIV_1
IOCONCLKDIV1
0x1
CLK_DIV_2
IOCONCLKDIV2
0x2
CLK_DIV_3
IOCONCLKDIV3
0x3
CLK_DIV_4
IOCONCLKDIV4
0x4
CLK_DIV_5
IOCONCLKDIV5
0x5
CLK_DIV_6
IOCONCLKDIV6
0x6
HYS
Hysteresis.
5
1
read-write
DISABLE
Disable
0
ENABLE
Enable
0x1
INV
Invert input
6
1
read-write
NOT_INVERTED
Input not inverted (HIGH on pin reads as 1 LOW on pin reads as 0).
0
INVERTED
Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
0x1
MODE
Selects function mode (on-chip pull-up/pull-down resistor control).
3
2
read-write
INACTIVE
Inactive. Inactive (no pull-down/pull-up resistor enabled).
0
PULL_DOWN
Pull-down. Pull-down resistor enabled.
0x1
PULL_UP
Pull-up. Pull-up resistor enabled.
0x2
REPEATER
Repeater. Repeater mode.
0x3
OD
Open-drain mode.
10
1
read-write
DISABLE
Disable.
0
ENABLED
Open-drain mode enabled. Remark: This is not a true open-drain mode.
0x1
S_MODE
Digital filter sample mode.
11
2
read-write
S_MODE_0
Bypass input filter.
0
S_MODE_1
1 clock cycle. Input pulses shorter than one filter clock are rejected.
0x1
S_MODE_2
2 clock cycles. Input pulses shorter than two filter clocks are rejected.
0x2
S_MODE_3
3 clock cycles. Input pulses shorter than three filter clocks are rejected.
0x3
MRT0
Multi-Rate Timer (MRT)
MRT
0x0
0x0
0xFC
registers
n
CHANNEL[0]-CTRL
MRT Control register. This register controls the MRT modes.
0x8
32
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
CHANNEL[0]-INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0x0
32
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
31
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
CHANNEL[0]-STAT
MRT Status register.
0xC
32
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
CHANNEL[0]-TIMER
MRT Timer register. This register reads the value of the down-counter.
0x4
32
read-only
n
0x0
0x0
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
31
read-only
CHANNEL[1]-CHANNEL[0]-CTRL
MRT Control register. This register controls the MRT modes.
0x18
32
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
CHANNEL[1]-CHANNEL[0]-INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0x10
32
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
31
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
CHANNEL[1]-CHANNEL[0]-STAT
MRT Status register.
0x1C
32
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
CHANNEL[1]-CHANNEL[0]-TIMER
MRT Timer register. This register reads the value of the down-counter.
0x14
32
read-only
n
0x0
0x0
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
31
read-only
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CTRL
MRT Control register. This register controls the MRT modes.
0x38
32
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0x30
32
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
31
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-STAT
MRT Status register.
0x3C
32
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TIMER
MRT Timer register. This register reads the value of the down-counter.
0x34
32
read-only
n
0x0
0x0
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
31
read-only
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CTRL
MRT Control register. This register controls the MRT modes.
0x68
32
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0x60
32
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
31
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-STAT
MRT Status register.
0x6C
32
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TIMER
MRT Timer register. This register reads the value of the down-counter.
0x64
32
read-only
n
0x0
0x0
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
31
read-only
CTRL
MRT Control register. This register controls the MRT modes.
0x8
32
read-write
n
0x0
0x0
INTEN
Enable the TIMERn interrupt.
0
1
read-write
DISABLED
Disabled. TIMERn interrupt is disabled.
0
ENABLED
Enabled. TIMERn interrupt is enabled.
0x1
MODE
Selects timer mode.
1
2
read-write
REPEAT_INTERRUPT_MODE
Repeat interrupt mode.
0
ONE_SHOT_INTERRUPT_MODE
One-shot interrupt mode.
0x1
ONE_SHOT_STALL_MODE
One-shot stall mode.
0x2
IDLE_CH
Idle channel register. This register returns the number of the first idle channel.
0xF4
32
read-only
n
0x0
0x0
CHAN
Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is positioned such that it can be used as an offset from the MRT base address in order to access the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See text above for more details.
4
4
read-only
INTVAL
MRT Time interval value register. This value is loaded into the TIMER register.
0x0
32
read-write
n
0x0
0x0
IVALUE
Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval.
0
31
read-write
LOAD
Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.
31
1
read-write
NO_FORCE_LOAD
No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.
0
FORCE_LOAD
Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
0x1
IRQ_FLAG
Global interrupt flag register
0xF8
32
read-write
n
0x0
0x0
GFLAG0
Monitors the interrupt flag of TIMER0.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
GFLAG1
Monitors the interrupt flag of TIMER1. See description of channel 0.
1
1
read-write
GFLAG2
Monitors the interrupt flag of TIMER2. See description of channel 0.
2
1
read-write
GFLAG3
Monitors the interrupt flag of TIMER3. See description of channel 0.
3
1
read-write
MODCFG
Module Configuration register. This register provides information about this particular MRT instance.
0xF0
32
read-write
n
0x0
0x0
NOB
Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
4
5
read-only
NOC
Identifies the number of channels in this MRT.(4 channels on this device.)
0
4
read-only
STAT
MRT Status register.
0xC
32
read-write
n
0x0
0x0
INTFLAG
Monitors the interrupt flag.
0
1
read-write
NO_PENDING_INTERRUPT
No pending interrupt. Writing a zero is equivalent to no operation.
0
PENDING_INTERRUPT
Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.
0x1
RUN
Indicates the state of TIMERn. This bit is read-only.
1
1
read-write
IDLE_STATE
Idle state. TIMERn is stopped.
0
RUNNING
Running. TIMERn is running.
0x1
TIMER
MRT Timer register. This register reads the value of the down-counter.
0x4
32
read-only
n
0x0
0x0
VALUE
Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF).
0
31
read-only
MTB
Micro Trace Buffer
MTB
0x0
0x0
0x10
registers
n
BASE
Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent.
0xC
32
read-only
n
0x0
0x0
BASE
The value provided is the value of the SRAMBASEADDR[31:0] signal.
0
32
read-only
FLOW
FLOW Register
0x8
32
read-write
n
0x0
0x0
AUTOHALT
If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request to the Cortex-M0+ processor by asserting the EDBGRQ signal.
1
1
read-write
AUTOSTOP
If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit is automatically set to 0. This stops tracing.
0
1
read-write
WATERMARK
WATERMARK value. This field contains an address in the same format as the POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by the AUTOHALT and AUTOSTOP bits are performed.
3
29
read-write
MASTER
MASTER Register
0x4
32
read-write
n
0x0
0x0
EN
Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH.
31
1
read-write
HALTREQ
Halt request bit. This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit can be automatically set to 1 using the FLOW.WATERMARK field.
9
1
read-write
MASK
This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect as the maximum.
0
5
read-write
RAMPRIV
SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal determines if an access is User or Privileged.
8
1
read-write
SFRWPRIV
Special Function Register Write Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this bit is 1, then only Privileged write accesses are permitted and User write accesses are ignored. The HPROT[1] signal determines if an access is User or Privileged.
7
1
read-write
TSTARTEN
Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs.
5
1
read-write
TSTOPEN
Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped.
6
1
read-write
POSITION
POSITION Register
0x0
32
read-write
n
0x0
0x0
POINTER
Trace packet location pointer. Because a packet consists of two words, the POINTER field is the location of the first word of a packet. This field contains bits [31:3] of the address, in the SRAM, where the next trace packet will be written. The field points to an unused location and is automatically incremented. A debug agent can calculate the system address, on the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P = POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value
3
29
read-write
WRAP
This bit is set to 1 automatically when the POINTER value wraps as determined by the MASTER.MASK field in the MASTER Trace Control Register.
2
1
read-write
PINT
Pin interrupt and pattern match (PINT)
PINT
0x0
0x0
0x30
registers
n
PIN_INT0
24
PIN_INT1
25
PIN_INT2
26
PIN_INT3
27
PIN_INT4
28
PIN_INT5
29
PIN_INT6
30
PIN_INT7
31
CIENF
Pin interrupt active level or falling edge interrupt clear register
0x18
32
write-only
n
0x0
0x0
CENAF
Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled.
0
8
write-only
CIENR
Pin interrupt level (rising edge interrupt) clear register
0xC
32
write-only
n
0x0
0x0
CENRL
Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt.
0
8
write-only
FALL
Pin interrupt falling edge register
0x20
32
read-write
n
0x0
0x0
FDET
Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin.
0
8
read-write
IENF
Pin interrupt active level or falling edge interrupt enable register
0x10
32
read-write
n
0x0
0x0
ENAF
Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH.
0
8
read-write
IENR
Pin interrupt level or rising edge interrupt enable register
0x4
32
read-write
n
0x0
0x0
ENRL
Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt.
0
8
read-write
ISEL
Pin Interrupt Mode register
0x0
32
read-write
n
0x0
0x0
PMODE
Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
0
8
read-write
IST
Pin interrupt status register
0x24
32
read-write
n
0x0
0x0
PSTAT
Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
0
8
read-write
PMCFG
Pattern match interrupt bit slice configuration register
0x30
32
read-write
n
0x0
0x0
CFG0
Specifies the match contribution condition for bit slice 0.
8
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG1
Specifies the match contribution condition for bit slice 1.
11
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG2
Specifies the match contribution condition for bit slice 2.
14
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG3
Specifies the match contribution condition for bit slice 3.
17
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG4
Specifies the match contribution condition for bit slice 4.
20
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG5
Specifies the match contribution condition for bit slice 5.
23
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG6
Specifies the match contribution condition for bit slice 6.
26
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
CFG7
Specifies the match contribution condition for bit slice 7.
29
3
read-write
CONSTANT_HIGH
Constant HIGH. This bit slice always contributes to a product term match.
0
STICKY_RISING_EDGE
Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x1
STICKY_FALLING_EDGE
Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x2
STICKY_RISING_FALLING_EDGE
Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.
0x3
HIGH_LEVEL
High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
0x4
LOW_LEVEL
Low level. Match occurs when there is a low level on the specified input.
0x5
CONSTANT_ZERO
Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
0x6
EVENT
Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.
0x7
PROD_ENDPTS0
Determines whether slice 0 is an endpoint.
0
1
read-write
NO_EFFECT
No effect. Slice 0 is not an endpoint.
0
ENDPOINT
endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS1
Determines whether slice 1 is an endpoint.
1
1
read-write
NO_EFFECT
No effect. Slice 1 is not an endpoint.
0
ENDPOINT
endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS2
Determines whether slice 2 is an endpoint.
2
1
read-write
NO_EFFECT
No effect. Slice 2 is not an endpoint.
0
ENDPOINT
endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS3
Determines whether slice 3 is an endpoint.
3
1
read-write
NO_EFFECT
No effect. Slice 3 is not an endpoint.
0
ENDPOINT
endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS4
Determines whether slice 4 is an endpoint.
4
1
read-write
NO_EFFECT
No effect. Slice 4 is not an endpoint.
0
ENDPOINT
endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS5
Determines whether slice 5 is an endpoint.
5
1
read-write
NO_EFFECT
No effect. Slice 5 is not an endpoint.
0
ENDPOINT
endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
0x1
PROD_ENDPTS6
Determines whether slice 6 is an endpoint.
6
1
read-write
NO_EFFECT
No effect. Slice 6 is not an endpoint.
0
ENDPOINT
endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
0x1
PMCTRL
Pattern match interrupt control register
0x28
32
read-write
n
0x0
0x0
ENA_RXEV
Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
1
1
read-write
DISABLED
Disabled. RXEV output to the CPU is disabled.
0
ENABLED
Enabled. RXEV output to the CPU is enabled.
0x1
PMAT
This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.
24
8
read-write
SEL_PMATCH
Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
0
1
read-write
PIN_INTERRUPT
Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
0
PATTERN_MATCH
Pattern match. Interrupts are driven in response to pattern matches.
0x1
PMSRC
Pattern match interrupt bit-slice source register
0x2C
32
read-write
n
0x0
0x0
SRC0
Selects the input source for bit slice 0
8
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
0x7
SRC1
Selects the input source for bit slice 1
11
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
0x7
SRC2
Selects the input source for bit slice 2
14
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
0x7
SRC3
Selects the input source for bit slice 3
17
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
0x7
SRC4
Selects the input source for bit slice 4
20
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
0x7
SRC5
Selects the input source for bit slice 5
23
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
0x7
SRC6
Selects the input source for bit slice 6
26
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
0x7
SRC7
Selects the input source for bit slice 7
29
3
read-write
INPUT0
Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
0
INPUT1
Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
0x1
INPUT2
Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.
0x2
INPUT3
Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.
0x3
INPUT4
Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.
0x4
INPUT5
Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.
0x5
INPUT6
Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
0x6
INPUT7
Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
0x7
RISE
Pin interrupt rising edge register
0x1C
32
read-write
n
0x0
0x0
RDET
Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
0
8
read-write
SIENF
Pin interrupt active level or falling edge interrupt set register
0x14
32
write-only
n
0x0
0x0
SETENAF
Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt.
0
8
write-only
SIENR
Pin interrupt level or rising edge interrupt set register
0x8
32
write-only
n
0x0
0x0
SETENRL
Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
0
8
write-only
PMU
PMU
PMU
0x0
0x0
0x18
registers
n
DPDCTRL
Deep power-down control register. Also includes bits for general purpose storage.
0x14
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
4
28
read-write
LPOSCDPDEN
causes the low-power oscillator to remain running during Deep power-down mode provided that bit 2 in this register is set as well. You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. Remark: Do not set this bit unless you use the self wake-up timer with the low-power oscillator clock source to wake up from Deep power-down mode.
3
1
read-write
DISABLED
Disabled.
0
ENABLED
Enabled.
0x1
LPOSCEN
Enable the low-power oscillator for use with the 10 kHz self wake-up timer clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC or the external clock input.
2
1
read-write
DISABLED
Disabled.
0
ENABLED
Enabled.
0x1
WAKEPAD_DISABLE
WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. Remark: Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is not used.
1
1
read-write
ENABLED
Enabled. The wake-up function is enabled on pin PIO0_4.
0
DISABLED
Disabled. Setting this bit disables the wake-up function on pin PIO0_4.
0x1
WAKEUPHYS
WAKEUP pin hysteresis enable
0
1
read-write
DISABLED
Disabled. Hysteresis for WAKEUP pin disabled.
0
ENABLED
Enabled. Hysteresis for WAKEUP pin enabled.
0x1
GPREG0
General purpose register N
0x4
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG1
General purpose register N
0x8
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG2
General purpose register N
0xC
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG3
General purpose register N
0x10
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[0]
General purpose register N
0x8
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[1]
General purpose register N
0x10
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[2]
General purpose register N
0x1C
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
GPREG[3]
General purpose register N
0x2C
32
read-write
n
0x0
0x0
GPDATA
Data retained during Deep power-down mode.
0
32
read-write
PCON
Power control register
0x0
32
read-write
n
0x0
0x0
DPDFLAG
Deep power-down flag
11
1
read-write
NOT_DEEP_POWER_DOWN
Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect.
0
DEEP_POWER_DOWN
Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.
0x1
NODPD
A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked.
3
1
read-write
PM
Power mode
0
3
read-write
DEFAULT
Default. The part is in active or sleep mode.
0
DEEP_SLEEP_MODE
Deep-sleep mode. ARM WFI will enter Deep-sleep mode.
0x1
POWER_DOWN_MODE
Power-down mode. ARM WFI will enter Power-down mode.
0x2
DEEP_POWER_DOWN_MODE
Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down).
0x3
SLEEPFLAG
Sleep mode flag
8
1
read-write
ACTIVE_MODE
Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect.
0
LOW_POWER_MODE
Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.
0x1
SCT0
SCTimer/PWM (SCT)
SCT
0x0
0x0
0x520
registers
n
SCT0
9
CAP0
SCT capture register of capture channel
CAP_MATCH
0x100
32
read-write
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAP1
SCT capture register of capture channel
CAP_MATCH
0x104
32
read-write
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAP2
SCT capture register of capture channel
CAP_MATCH
0x108
32
read-write
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAP3
SCT capture register of capture channel
CAP_MATCH
0x10C
32
read-write
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAP4
SCT capture register of capture channel
CAP_MATCH
0x110
32
read-write
n
0x0
0x0
CAPn_H
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured.
16
16
read-write
CAPn_L
When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured.
0
16
read-write
CAPCTRL0
SCT capture control register
CAPCTRL_MATCHREL
0x200
32
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCTRL1
SCT capture control register
CAPCTRL_MATCHREL
0x204
32
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCTRL2
SCT capture control register
CAPCTRL_MATCHREL
0x208
32
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCTRL3
SCT capture control register
CAPCTRL_MATCHREL
0x20C
32
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CAPCTRL4
SCT capture control register
CAPCTRL_MATCHREL
0x210
32
read-write
n
0x0
0x0
CAPCONn_H
If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
16
16
read-write
CAPCONn_L
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT.
0
16
read-write
CONEN
SCT conflict interrupt enable register
0xF8
32
read-write
n
0x0
0x0
NCEN
The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0
4
read-write
CONFIG
SCT configuration register
0x0
32
read-write
n
0x0
0x0
AUTOLIMIT_H
A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
18
1
read-write
AUTOLIMIT_L
A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
17
1
read-write
CKSEL
SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.
3
4
read-write
INPUT_0_RISING_EDGES
Rising edges on input 0.
0
INPUT_0_FALLING_EDGE
Falling edges on input 0.
0x1
INPUT_1_RISING_EDGES
Rising edges on input 1.
0x2
INPUT_1_FALLING_EDGE
Falling edges on input 1.
0x3
INPUT_2_RISING_EDGES
Rising edges on input 2.
0x4
INPUT_2_FALLING_EDGE
Falling edges on input 2.
0x5
INPUT_3_RISING_EDGES
Rising edges on input 3.
0x6
INPUT_3_FALLING_EDGE
Falling edges on input 3.
0x7
CLKMODE
SCT clock mode
1
2
read-write
SYSTEM_CLOCK_MODE
System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
0
SAMPLED_SYSTEM_CLOCK_MODE
Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.
0x1
SCT_INPUT_CLOCK_MODE
SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
0x2
ASYNCHRONOUS_MODE
Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.
0x3
INSYNC
Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field.
9
8
read-write
NORELOAD_H
A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.
8
1
read-write
NORELOAD_L
A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
7
1
read-write
UNIFY
SCT operation
0
1
read-write
DUAL_COUNTER
The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
0
UNIFIED_COUNTER
The SCT operates as a unified 32-bit counter.
0x1
CONFLAG
SCT conflict flag register
0xFC
32
read-write
n
0x0
0x0
BUSERRH
The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted.
31
1
read-write
BUSERRL
The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful.
30
1
read-write
NCFLAG
Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0
4
read-write
COUNT
SCT counter register
0x40
32
read-write
n
0x0
0x0
CTR_H
When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter.
16
16
read-write
CTR_L
When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter.
0
16
read-write
CTRL
SCT control register
0x4
32
read-write
n
0x0
0x0
BIDIR_H
Direction select
20
1
read-write
UP
The H counter counts up to its limit condition, then is cleared to zero.
0
UP_DOWN
The H counter counts up to its limit, then counts down to a limit condition or to 0.
0x1
BIDIR_L
L or unified counter direction select
4
1
read-write
UP
Up. The counter counts up to a limit condition, then is cleared to zero.
0
UP_DOWN
Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
0x1
CLRCTR_H
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
19
1
read-write
CLRCTR_L
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
3
1
read-write
DOWN_H
This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
16
1
read-write
DOWN_L
This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0.
0
1
read-write
HALT_H
When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset.
18
1
read-write
HALT_L
When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset.
2
1
read-write
PRE_H
Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
21
8
read-write
PRE_L
Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
5
8
read-write
STOP_H
When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes.
17
1
read-write
STOP_L
When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes.
1
1
read-write
EVEN
SCT event interrupt enable register
0xF0
32
read-write
n
0x0
0x0
IEN
The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
6
read-write
EVFLAG
SCT event flag register
0xF4
32
read-write
n
0x0
0x0
FLAG
Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
6
read-write
EV[0]-EV_CTRL
SCT event control register 0
0x304
32
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
2
read-write
OR
OR. The event occurs when either the specified match or I/O condition occurs.
0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition only.
0x2
AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
2
read-write
DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0
COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
1
read-write
L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0
H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
0x1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
2
read-write
LOW
LOW
0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
4
read-write
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
1
read-write
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
read-write
OUTSEL
Input/output select
5
1
read-write
INPUT
Selects the inputs selected by IOSEL.
0
OUTPUT
Selects the outputs selected by IOSEL.
0x1
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
1
read-write
ADD
STATEV value is added into STATE (the carry-out is ignored).
0
LOAD
STATEV value is loaded into STATE.
0x1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
5
read-write
EV[0]-EV_STATE
SCT event state register 0
0x300
32
read-write
n
0x0
0x0
STATEMSK0
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0
1
read-write
STATEMSK1
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
1
1
read-write
EV[1]-EV[0]-EV_CTRL
SCT event control register 0
0x60C
32
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
2
read-write
OR
OR. The event occurs when either the specified match or I/O condition occurs.
0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition only.
0x2
AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
2
read-write
DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0
COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
1
read-write
L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0
H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
0x1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
2
read-write
LOW
LOW
0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
4
read-write
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
1
read-write
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
read-write
OUTSEL
Input/output select
5
1
read-write
INPUT
Selects the inputs selected by IOSEL.
0
OUTPUT
Selects the outputs selected by IOSEL.
0x1
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
1
read-write
ADD
STATEV value is added into STATE (the carry-out is ignored).
0
LOAD
STATEV value is loaded into STATE.
0x1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
5
read-write
EV[1]-EV[0]-EV_STATE
SCT event state register 0
0x608
32
read-write
n
0x0
0x0
STATEMSK0
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0
1
read-write
STATEMSK1
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
1
1
read-write
EV[2]-EV[1]-EV[0]-EV_CTRL
SCT event control register 0
0x91C
32
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
2
read-write
OR
OR. The event occurs when either the specified match or I/O condition occurs.
0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition only.
0x2
AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
2
read-write
DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0
COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
1
read-write
L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0
H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
0x1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
2
read-write
LOW
LOW
0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
4
read-write
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
1
read-write
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
read-write
OUTSEL
Input/output select
5
1
read-write
INPUT
Selects the inputs selected by IOSEL.
0
OUTPUT
Selects the outputs selected by IOSEL.
0x1
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
1
read-write
ADD
STATEV value is added into STATE (the carry-out is ignored).
0
LOAD
STATEV value is loaded into STATE.
0x1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
5
read-write
EV[2]-EV[1]-EV[0]-EV_STATE
SCT event state register 0
0x918
32
read-write
n
0x0
0x0
STATEMSK0
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0
1
read-write
STATEMSK1
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
1
1
read-write
EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
SCT event control register 0
0xC34
32
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
2
read-write
OR
OR. The event occurs when either the specified match or I/O condition occurs.
0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition only.
0x2
AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
2
read-write
DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0
COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
1
read-write
L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0
H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
0x1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
2
read-write
LOW
LOW
0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
4
read-write
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
1
read-write
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
read-write
OUTSEL
Input/output select
5
1
read-write
INPUT
Selects the inputs selected by IOSEL.
0
OUTPUT
Selects the outputs selected by IOSEL.
0x1
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
1
read-write
ADD
STATEV value is added into STATE (the carry-out is ignored).
0
LOAD
STATEV value is loaded into STATE.
0x1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
5
read-write
EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
SCT event state register 0
0xC30
32
read-write
n
0x0
0x0
STATEMSK0
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0
1
read-write
STATEMSK1
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
1
1
read-write
EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
SCT event control register 0
0xF54
32
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
2
read-write
OR
OR. The event occurs when either the specified match or I/O condition occurs.
0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition only.
0x2
AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
2
read-write
DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0
COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
1
read-write
L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0
H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
0x1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
2
read-write
LOW
LOW
0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
4
read-write
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
1
read-write
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
read-write
OUTSEL
Input/output select
5
1
read-write
INPUT
Selects the inputs selected by IOSEL.
0
OUTPUT
Selects the outputs selected by IOSEL.
0x1
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
1
read-write
ADD
STATEV value is added into STATE (the carry-out is ignored).
0
LOAD
STATEV value is loaded into STATE.
0x1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
5
read-write
EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
SCT event state register 0
0xF50
32
read-write
n
0x0
0x0
STATEMSK0
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0
1
read-write
STATEMSK1
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
1
1
read-write
EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_CTRL
SCT event control register 0
0x127C
32
read-write
n
0x0
0x0
COMBMODE
Selects how the specified match and I/O condition are used and combined.
12
2
read-write
OR
OR. The event occurs when either the specified match or I/O condition occurs.
0
MATCH
MATCH. Uses the specified match only.
0x1
IO
IO. Uses the specified I/O condition only.
0x2
AND
AND. The event occurs when the specified match and I/O condition occur simultaneously.
0x3
DIRECTION
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
21
2
read-write
DIRECTION_INDEPENDENT
Direction independent. This event is triggered regardless of the count direction.
0
COUNTING_UP
Counting up. This event is triggered only during up-counting when BIDIR = 1.
0x1
COUNTING_DOWN
Counting down. This event is triggered only during down-counting when BIDIR = 1.
0x2
HEVENT
Select L/H counter. Do not set this bit if UNIFY = 1.
4
1
read-write
L_COUNTER
Selects the L state and the L match register selected by MATCHSEL.
0
H_COUNTER
Selects the H state and the H match register selected by MATCHSEL.
0x1
IOCOND
Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
10
2
read-write
LOW
LOW
0
RISE
Rise
0x1
FALL
Fall
0x2
HIGH
HIGH
0x3
IOSEL
Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
6
4
read-write
MATCHMEM
If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
20
1
read-write
MATCHSEL
Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
0
4
read-write
OUTSEL
Input/output select
5
1
read-write
INPUT
Selects the inputs selected by IOSEL.
0
OUTPUT
Selects the outputs selected by IOSEL.
0x1
STATELD
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
14
1
read-write
ADD
STATEV value is added into STATE (the carry-out is ignored).
0
LOAD
STATEV value is loaded into STATE.
0x1
STATEV
This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
15
5
read-write
EV[5]-EV[4]-EV[3]-EV[2]-EV[1]-EV[0]-EV_STATE
SCT event state register 0
0x1278
32
read-write
n
0x0
0x0
STATEMSK0
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
0
1
read-write
STATEMSK1
If bit m is one, event n happens in state m of the counter selected by the HEVENT bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of bits = number of states in this SCT.
1
1
read-write
HALT
SCT halt event select register
0xC
32
read-write
n
0x0
0x0
HALTMSK_H
If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
16
6
read-write
HALTMSK_L
If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
6
read-write
INPUT
SCT input register
0x48
32
read-write
n
0x0
0x0
AIN0
Input 0 state. Input 0 state on the last SCT clock edge.
0
1
read-only
AIN1
Input 1 state. Input 1 state on the last SCT clock edge.
1
1
read-only
AIN2
Input 2 state. Input 2 state on the last SCT clock edge.
2
1
read-only
AIN3
Input 3 state. Input 3 state on the last SCT clock edge.
3
1
read-only
SIN0
Input 0 state. Input 0 state following the synchronization specified by INSYNC.
16
1
read-only
SIN1
Input 1 state. Input 1 state following the synchronization specified by INSYNC.
17
1
read-only
SIN2
Input 2 state. Input 2 state following the synchronization specified by INSYNC.
18
1
read-only
SIN3
Input 3 state. Input 3 state following the synchronization specified by INSYNC.
19
1
read-only
LIMIT
SCT limit event select register
0x8
32
read-write
n
0x0
0x0
LIMMSK_H
If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
16
6
read-write
LIMMSK_L
If bit n is one, event n is used as a counter limit for the L or unified counter (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
6
read-write
MATCH0
SCT match value register of match channels
CAP_MATCH
0x100
32
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCH1
SCT match value register of match channels
CAP_MATCH
0x104
32
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCH2
SCT match value register of match channels
CAP_MATCH
0x108
32
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCH3
SCT match value register of match channels
CAP_MATCH
0x10C
32
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCH4
SCT match value register of match channels
CAP_MATCH
0x110
32
read-write
n
0x0
0x0
MATCHn_H
When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter.
16
16
read-write
MATCHn_L
When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter.
0
16
read-write
MATCHREL0
SCT match reload value register
CAPCTRL_MATCHREL
0x200
32
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
MATCHREL1
SCT match reload value register
CAPCTRL_MATCHREL
0x204
32
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
MATCHREL2
SCT match reload value register
CAPCTRL_MATCHREL
0x208
32
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
MATCHREL3
SCT match reload value register
CAPCTRL_MATCHREL
0x20C
32
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
MATCHREL4
SCT match reload value register
CAPCTRL_MATCHREL
0x210
32
read-write
n
0x0
0x0
RELOADn_H
When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register.
16
16
read-write
RELOADn_L
When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn register.
0
16
read-write
OUTPUT
SCT output register
0x50
32
read-write
n
0x0
0x0
OUT
Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of outputs in this SCT.
0
4
read-write
OUTPUTDIRCTRL
SCT output counter direction control register
0x54
32
read-write
n
0x0
0x0
SETCLR0
Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
0
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR1
Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
2
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR2
Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
4
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
SETCLR3
Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
6
2
read-write
INDEPENDENT
Set and clear do not depend on the direction of any counter.
0
L_REVERSED
Set and clear are reversed when counter L or the unified counter is counting down.
0x1
H_REVERSED
Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
0x2
OUT[0]-OUT_CLR
SCT output 0 clear register
0x504
32
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
6
read-write
OUT[0]-OUT_SET
SCT output 0 set register
0x500
32
read-write
n
0x0
0x0
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
6
read-write
OUT[1]-OUT[0]-OUT_CLR
SCT output 0 clear register
0xA0C
32
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
6
read-write
OUT[1]-OUT[0]-OUT_SET
SCT output 0 set register
0xA08
32
read-write
n
0x0
0x0
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
6
read-write
OUT[2]-OUT[1]-OUT[0]-OUT_CLR
SCT output 0 clear register
0xF1C
32
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
6
read-write
OUT[2]-OUT[1]-OUT[0]-OUT_SET
SCT output 0 set register
0xF18
32
read-write
n
0x0
0x0
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
6
read-write
OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_CLR
SCT output 0 clear register
0x1434
32
read-write
n
0x0
0x0
CLR
A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
6
read-write
OUT[3]-OUT[2]-OUT[1]-OUT[0]-OUT_SET
SCT output 0 set register
0x1430
32
read-write
n
0x0
0x0
SET
A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the counter is used in bi-directional mode, it is possible to reverse the action specified by the output set and clear registers when counting down, See the OUTPUTCTRL register.
0
6
read-write
REGMODE
SCT match/capture mode register
0x4C
32
read-write
n
0x0
0x0
REGMOD_H
Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match registers. 1 = register operates as capture registers.
16
5
read-write
REGMOD_L
Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as match register. 1 = register operates as capture register.
0
5
read-write
RES
SCT conflict resolution register
0x58
32
read-write
n
0x0
0x0
O0RES
Effect of simultaneous set and clear on output 0.
0
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR0 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O1RES
Effect of simultaneous set and clear on output 1.
2
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR1 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O2RES
Effect of simultaneous set and clear on output 2.
4
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output n (or set based on the SETCLR2 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
O3RES
Effect of simultaneous set and clear on output 3.
6
2
read-write
NO_CHANGE
No change.
0
SET
Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
0x1
CLEAR
Clear output (or set based on the SETCLR3 field).
0x2
TOGGLE_OUTPUT
Toggle output.
0x3
START
SCT start event select register
0x14
32
read-write
n
0x0
0x0
STARTMSK_H
If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
16
6
read-write
STARTMSK_L
If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
6
read-write
STATE
SCT state register
0x44
32
read-write
n
0x0
0x0
STATE_H
State variable.
16
5
read-write
STATE_L
State variable.
0
5
read-write
STOP
SCT stop event select register
0x10
32
read-write
n
0x0
0x0
STOPMSK_H
If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
16
6
read-write
STOPMSK_L
If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
0
6
read-write
SPI0
Serial Peripheral Interfaces (SPI)
SPI
0x0
0x0
0x2C
registers
n
SPI0
0
CFG
SPI Configuration register
0x0
32
read-write
n
0x0
0x0
CPHA
Clock Phase select.
4
1
read-write
CHANGE
Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0
CAPTURE
Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
0x1
CPOL
Clock Polarity select.
5
1
read-write
LOW
Low. The rest state of the clock (between transfers) is low.
0
HIGH
High. The rest state of the clock (between transfers) is high.
0x1
ENABLE
SPI enable.
0
1
read-write
DISABLED
Disabled. The SPI is disabled and the internal state machine and counters are reset.
0
ENABLED
Enabled. The SPI is enabled for operation.
0x1
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
7
1
read-write
DISABLED
Disabled.
0
ENABLED
Enabled.
0x1
LSBF
LSB First mode enable.
3
1
read-write
STANDARD
Standard. Data is transmitted and received in standard MSB first order.
0
REVERSE
Reverse. Data is transmitted and received in reverse order (LSB first).
0x1
MASTER
Master mode select.
2
1
read-write
SLAVE_MODE
Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0
MASTER_MODE
Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
0x1
SPOL0
SSEL0 Polarity select.
8
1
read-write
LOW
Low. The SSEL0 pin is active low.
0
HIGH
High. The SSEL0 pin is active high.
0x1
DIV
SPI clock Divider
0x24
32
read-write
n
0x0
0x0
DIVVAL
Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.
0
16
read-write
DLY
SPI Delay register
0x4
32
read-write
n
0x0
0x0
FRAME_DELAY
If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
8
4
read-write
POST_DELAY
Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
4
4
read-write
PRE_DELAY
Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0
4
read-write
TRANSFER_DELAY
Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
12
4
read-write
INTENCLR
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
0x10
32
write-only
n
0x0
0x0
RXOVEN
Writing 1 clears the corresponding bits in the INTENSET register.
2
1
write-only
RXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
1
write-only
SSAEN
Writing 1 clears the corresponding bits in the INTENSET register.
4
1
write-only
SSDEN
Writing 1 clears the corresponding bits in the INTENSET register.
5
1
write-only
TXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
1
1
write-only
TXUREN
Writing 1 clears the corresponding bits in the INTENSET register.
3
1
write-only
INTENSET
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
n
0x0
0x0
RXOVEN
Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
2
1
read-write
RXOVEN_0
No interrupt will be generated when a receiver overrun occurs.
0
RXOVEN_1
An interrupt will be generated if a receiver overrun occurs.
0x1
RXRDYEN
Determines whether an interrupt occurs when receiver data is available.
0
1
read-write
RXRDYEN_0
No interrupt will be generated when receiver data is available.
0
RXRDYEN_1
An interrupt will be generated when receiver data is available in the RXDAT register.
0x1
SSAEN
Determines whether an interrupt occurs when the Slave Select is asserted.
4
1
read-write
SSAEN_0
No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0
SSAEN_1
An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1
SSDEN
Determines whether an interrupt occurs when the Slave Select is deasserted.
5
1
read-write
SSDEN_0
No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0
SSDEN_1
An interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1
TXRDYEN
Determines whether an interrupt occurs when the transmitter holding register is available.
1
1
read-write
TXRDYEN_0
No interrupt will be generated when the transmitter holding register is available.
0
TXRDYEN_1
An interrupt will be generated when data may be written to TXDAT.
0x1
TXUREN
Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
3
1
read-write
TXUREN_0
No interrupt will be generated when the transmitter underruns.
0
TXUREN_1
An interrupt will be generated if the transmitter underruns.
0x1
INTSTAT
SPI Interrupt Status
0x28
32
read-write
n
0x0
0x0
RXOV
Receiver Overrun interrupt flag.
2
1
read-only
RXRDY
Receiver Ready flag.
0
1
read-only
SSA
Slave Select Assert.
4
1
read-only
SSD
Slave Select Deassert.
5
1
read-only
TXRDY
Transmitter Ready flag.
1
1
read-only
TXUR
Transmitter Underrun interrupt flag.
3
1
read-only
RXDAT
SPI Receive Data
0x14
32
read-only
n
0x0
0x0
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
read-only
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
1
read-only
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
1
read-only
STAT
SPI Status. Some status flags can be cleared by writing a 1 to that bit position
0x8
32
read-write
n
0x0
0x0
ENDTRANSFER
End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
7
1
read-write
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
8
1
read-only
RXOV
Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
2
1
write-only
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
0
1
read-only
SSA
Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
4
1
write-only
SSD
Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
5
1
write-only
STALLED
Stalled status flag. This indicates whether the SPI is currently in a stall condition.
6
1
read-only
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
1
1
read-only
TXUR
Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
3
1
write-only
TXCTL
SPI Transmit Control
0x20
32
read-write
n
0x0
0x0
EOF
End of Frame.
21
1
read-write
EOT
End of Transfer.
20
1
read-write
LEN
Data transfer Length.
24
4
read-write
RXIGNORE
Receive Ignore.
22
1
read-write
TXSSEL0_N
Transmit Slave Select 0.
16
1
read-write
TXDAT
SPI Transmit Data.
0x1C
32
read-write
n
0x0
0x0
DATA
Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
0
16
read-write
TXDATCTL
SPI Transmit Data with Control
0x18
32
read-write
n
0x0
0x0
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
1
read-write
Data_not_EOF
This piece of data transmitted is not treated as the end of a frame.
0
Data_EOF
This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
0x1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
1
read-write
SSEL_deasserted
This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0
SSEL_not_deasserted
This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
0x1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
4
read-write
LEN_0
no description available
0
LEN_1
Data transfer is 1 bit in length.
0x1
LEN_2
Data transfer is 2 bit in length.
0x2
LEN_3
Data transfer is 3 bit in length.
0x3
LEN_4
Data transfer is 4 bit in length.
0x4
LEN_5
Data transfer is 5 bit in length.
0x5
LEN_6
Data transfer is 6 bit in length.
0x6
LEN_7
Data transfer is 7 bit in length.
0x7
LEN_8
Data transfer is 8 bit in length.
0x8
LEN_9
Data transfer is 9 bit in length.
0x9
LEN_10
Data transfer is 10 bit in length.
0xA
LEN_11
Data transfer is 11 bit in length.
0xB
LEN_12
Data transfer is 12 bit in length.
0xC
LEN_13
Data transfer is 13 bit in length.
0xD
LEN_14
Data transfer is 14 bit in length.
0xE
LEN_15
Data transfer is 15 bit in length.
0xF
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
22
1
read-write
Read_received_data
Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0
Ignore_received_data
Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
0x1
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
read-write
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.
16
1
read-write
TXSSEL0_N_0
SSEL0 asserted.
0
TXSSEL0_N_1
SSEL0 not asserted.
0x1
SPI1
Serial Peripheral Interfaces (SPI)
SPI
0x0
0x0
0x2C
registers
n
SPI1
1
CFG
SPI Configuration register
0x0
32
read-write
n
0x0
0x0
CPHA
Clock Phase select.
4
1
read-write
CHANGE
Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.
0
CAPTURE
Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.
0x1
CPOL
Clock Polarity select.
5
1
read-write
LOW
Low. The rest state of the clock (between transfers) is low.
0
HIGH
High. The rest state of the clock (between transfers) is high.
0x1
ENABLE
SPI enable.
0
1
read-write
DISABLED
Disabled. The SPI is disabled and the internal state machine and counters are reset.
0
ENABLED
Enabled. The SPI is enabled for operation.
0x1
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.
7
1
read-write
DISABLED
Disabled.
0
ENABLED
Enabled.
0x1
LSBF
LSB First mode enable.
3
1
read-write
STANDARD
Standard. Data is transmitted and received in standard MSB first order.
0
REVERSE
Reverse. Data is transmitted and received in reverse order (LSB first).
0x1
MASTER
Master mode select.
2
1
read-write
SLAVE_MODE
Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
0
MASTER_MODE
Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
0x1
SPOL0
SSEL0 Polarity select.
8
1
read-write
LOW
Low. The SSEL0 pin is active low.
0
HIGH
High. The SSEL0 pin is active high.
0x1
DIV
SPI clock Divider
0x24
32
read-write
n
0x0
0x0
DIVVAL
Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.
0
16
read-write
DLY
SPI Delay register
0x4
32
read-write
n
0x0
0x0
FRAME_DELAY
If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
8
4
read-write
POST_DELAY
Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
4
4
read-write
PRE_DELAY
Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted.
0
4
read-write
TRANSFER_DELAY
Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times.
12
4
read-write
INTENCLR
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
0x10
32
write-only
n
0x0
0x0
RXOVEN
Writing 1 clears the corresponding bits in the INTENSET register.
2
1
write-only
RXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
0
1
write-only
SSAEN
Writing 1 clears the corresponding bits in the INTENSET register.
4
1
write-only
SSDEN
Writing 1 clears the corresponding bits in the INTENSET register.
5
1
write-only
TXRDYEN
Writing 1 clears the corresponding bits in the INTENSET register.
1
1
write-only
TXUREN
Writing 1 clears the corresponding bits in the INTENSET register.
3
1
write-only
INTENSET
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
n
0x0
0x0
RXOVEN
Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
2
1
read-write
RXOVEN_0
No interrupt will be generated when a receiver overrun occurs.
0
RXOVEN_1
An interrupt will be generated if a receiver overrun occurs.
0x1
RXRDYEN
Determines whether an interrupt occurs when receiver data is available.
0
1
read-write
RXRDYEN_0
No interrupt will be generated when receiver data is available.
0
RXRDYEN_1
An interrupt will be generated when receiver data is available in the RXDAT register.
0x1
SSAEN
Determines whether an interrupt occurs when the Slave Select is asserted.
4
1
read-write
SSAEN_0
No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0
SSAEN_1
An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
0x1
SSDEN
Determines whether an interrupt occurs when the Slave Select is deasserted.
5
1
read-write
SSDEN_0
No interrupt will be generated when all asserted Slave Selects transition to deasserted.
0
SSDEN_1
An interrupt will be generated when all asserted Slave Selects transition to deasserted.
0x1
TXRDYEN
Determines whether an interrupt occurs when the transmitter holding register is available.
1
1
read-write
TXRDYEN_0
No interrupt will be generated when the transmitter holding register is available.
0
TXRDYEN_1
An interrupt will be generated when data may be written to TXDAT.
0x1
TXUREN
Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
3
1
read-write
TXUREN_0
No interrupt will be generated when the transmitter underruns.
0
TXUREN_1
An interrupt will be generated if the transmitter underruns.
0x1
INTSTAT
SPI Interrupt Status
0x28
32
read-write
n
0x0
0x0
RXOV
Receiver Overrun interrupt flag.
2
1
read-only
RXRDY
Receiver Ready flag.
0
1
read-only
SSA
Slave Select Assert.
4
1
read-only
SSD
Slave Select Deassert.
5
1
read-only
TXRDY
Transmitter Ready flag.
1
1
read-only
TXUR
Transmitter Underrun interrupt flag.
3
1
read-only
RXDAT
SPI Receive Data
0x14
32
read-only
n
0x0
0x0
RXDAT
Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
0
16
read-only
RXSSEL0_N
Slave Select for receive. This field allows the state of the SSEL0 pin to be saved along with received data. The value will reflect the SSEL0 pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG.
16
1
read-only
SOT
Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the transfer length is greater than 16 bit.
20
1
read-only
STAT
SPI Status. Some status flags can be cleared by writing a 1 to that bit position
0x8
32
read-write
n
0x0
0x0
ENDTRANSFER
End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
7
1
read-write
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data.
8
1
read-only
RXOV
Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set.
2
1
write-only
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register.
0
1
read-only
SSA
Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software.
4
1
write-only
SSD
Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software.
5
1
write-only
STALLED
Stalled status flag. This indicates whether the SPI is currently in a stall condition.
6
1
read-only
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register.
1
1
read-only
TXUR
Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set.
3
1
write-only
TXCTL
SPI Transmit Control
0x20
32
read-write
n
0x0
0x0
EOF
End of Frame.
21
1
read-write
EOT
End of Transfer.
20
1
read-write
LEN
Data transfer Length.
24
4
read-write
RXIGNORE
Receive Ignore.
22
1
read-write
TXSSEL0_N
Transmit Slave Select 0.
16
1
read-write
TXDAT
SPI Transmit Data.
0x1C
32
read-write
n
0x0
0x0
DATA
Transmit Data. This field provides from 4 to 16 bits of data to be transmitted.
0
16
read-write
TXDATCTL
SPI Transmit Data with Control
0x18
32
read-write
n
0x0
0x0
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
21
1
read-write
Data_not_EOF
This piece of data transmitted is not treated as the end of a frame.
0
Data_EOF
This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted.
0x1
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.
20
1
read-write
SSEL_deasserted
This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
0
SSEL_not_deasserted
This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
0x1
LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length.
24
4
read-write
LEN_0
no description available
0
LEN_1
Data transfer is 1 bit in length.
0x1
LEN_2
Data transfer is 2 bit in length.
0x2
LEN_3
Data transfer is 3 bit in length.
0x3
LEN_4
Data transfer is 4 bit in length.
0x4
LEN_5
Data transfer is 5 bit in length.
0x5
LEN_6
Data transfer is 6 bit in length.
0x6
LEN_7
Data transfer is 7 bit in length.
0x7
LEN_8
Data transfer is 8 bit in length.
0x8
LEN_9
Data transfer is 9 bit in length.
0x9
LEN_10
Data transfer is 10 bit in length.
0xA
LEN_11
Data transfer is 11 bit in length.
0xB
LEN_12
Data transfer is 12 bit in length.
0xC
LEN_13
Data transfer is 13 bit in length.
0xD
LEN_14
Data transfer is 14 bit in length.
0xE
LEN_15
Data transfer is 15 bit in length.
0xF
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.
22
1
read-write
Read_received_data
Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received.
0
Ignore_received_data
Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.
0x1
TXDAT
Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
0
16
read-write
TXSSEL0_N
Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.
16
1
read-write
TXSSEL0_N_0
SSEL0 asserted.
0
TXSSEL0_N_1
SSEL0 not asserted.
0x1
SWM0
LPC81x SWM
SWM
0x0
0x0
0x1C4
registers
n
PINASSIGN0
Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS.
PINASSIGN_PINASSIGN_DATA
0x0
32
read-write
n
0x0
0x0
U0_CTS_I
U0_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
U0_RTS_O
U0_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
U0_RXD_I
U0_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
U0_TXD_O
U0_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
PINASSIGN1
Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_RTS.
PINASSIGN_PINASSIGN_DATA
0x4
32
read-write
n
0x0
0x0
U0_SCLK_IO
U0_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
U1_RTS_O
U1_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
U1_RXD_I
U1_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
U1_TXD_O
U1_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
PINASSIGN2
Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK, U2_TXD, U2_RXD.
PINASSIGN_PINASSIGN_DATA
0x8
32
read-write
n
0x0
0x0
U1_CTS_I
U1_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
U1_SCLK_IO
U1_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
U2_RXD_I
U2_RXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
U2_TXD_O
U2_TXD function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
PINASSIGN3
Pin assign register 3. Assign movable function U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK.
PINASSIGN_PINASSIGN_DATA
0xC
32
read-write
n
0x0
0x0
SPI0_SCK_IO
SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
U2_CTS_I
U2_CTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
U2_RTS_O
U2_RTS function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
U2_SCLK_IO
U2_SCLK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
PINASSIGN4
Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO,SPI0_SSEL, SPI1_SCK.
PINASSIGN_PINASSIGN_DATA
0x10
32
read-write
n
0x0
0x0
SPI0_MISO_IO
SPI0_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
SPI0_MOSI_IO
SPI0_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
SPI0_SSEL_IO
SPI0_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
SPI1_SCK_IO
SPI1_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
PINASSIGN5
Pin assign register 5. Assign movable functions SPI1_MOSI, SPI1_MISO,SPI1_SSEL, CTIN_0
PINASSIGN_PINASSIGN_DATA
0x14
32
read-write
n
0x0
0x0
CTIN_0_I
CTIN_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
SPI1_MISO_IO
SPI1_MISIO function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
SPI1_MOSI_IO
SPI1_MOSI function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
SPI1_SSEL_IO
SPI1_SSEL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
PINASSIGN6
Pin assign register 6. Assign movable functions CTIN_1, CTIN_2, CTIN_3,CTOUT_0.
PINASSIGN_PINASSIGN_DATA
0x18
32
read-write
n
0x0
0x0
CTIN_1_I
CTIN_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
CTIN_2_I
CTIN_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
CTIN_3_I
CTIN_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
CTOUT_0_O
CTOUT_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
PINASSIGN7
Pin assign register 7. Assign movable functions CTOUT_1, CTOUT_2, CTOUT_3,I2C_SDA.
PINASSIGN_PINASSIGN_DATA
0x1C
32
read-write
n
0x0
0x0
CTOUT_1_O
CTOUT_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
CTOUT_2_O
CTOUT_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
CTOUT_3_O
CTOUT_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
I2C_SDA_IO
I2C_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
PINASSIGN8
Pin assign register 8. Assign movable functions I2C_SCL, ACMP_O, CLKOUT,GPIO_INT_BMAT.
PINASSIGN_PINASSIGN_DATA
0x20
32
read-write
n
0x0
0x0
ACMP_O_O
ACMP_O_O function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
8
8
read-write
CLKOUT_O
CLKOUT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
16
8
read-write
GPIO_INT_BMAT_O
GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
24
8
read-write
I2C_SCL_IO
I2C_SCL function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0(= 0) to PIO0_17 (= 0x11).
0
8
read-write
PINASSIGN_DATA0
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x0
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA1
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x4
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA2
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x8
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA3
Pin assign register
PINASSIGN_PINASSIGN_DATA
0xC
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA4
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x10
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA5
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x14
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA6
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x18
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA7
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x1C
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINASSIGN_DATA8
Pin assign register
PINASSIGN_PINASSIGN_DATA
0x20
32
read-write
n
0x0
0x0
DATA0
T0_MAT3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
0
8
read-write
DATA1
T0_CAP0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
8
8
read-write
DATA2
T0_CAP1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
16
8
read-write
DATA3
T0_CAP2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_31 (= 0x1F) and from PIO1_0 (=0x20) to PIO1_21(=0x35).
24
8
read-write
PINENABLE0
Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP and so on.
0x1C0
32
read-write
n
0x0
0x0
ACMP_I1
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.
0
1
read-write
ENABLED
Enable ACMP_I1. This function is enabled on pin PIO0_0.
0
DISABLED
Disable ACMP_I1. GPIO function PIO0_0 (default) or any other movable function can be assigned to pin PIO0_0.
0x1
ACMP_I2
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use ACMP_I2, disable the CLKIN function in bit 7 of this register and enable ACMP_I2.
1
1
read-write
ACMP_I2_0
Enable ACMP_I2. This function is enabled on pin PIO0_1.
0
ACMP_I2_1
Disable ACMP_I2. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin PIO0_1.
0x1
CLKIN
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use CLKIN, disable ACMP_I2 in bit 1 of this register and enable CLKIN.
7
1
read-write
ENABLED
Enable CLKIN. This function is enabled on pin PIO0_1.
0
DISABLED
Disable CLKIN. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin CLKIN.
0x1
RESET
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.
6
1
read-write
ENABLED
Enable RESET. This function is enabled on pin PIO0_5.
0
DISABLED
Disable RESET. GPIO function PIO0_5 is selected on this pin. Any other movable function can be assigned to pin PIO0_5.
0x1
RESETN
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.
6
1
read-write
ENABLED
Enable RESETN. This function is enabled on pin PIO0_5.
0
DISABLED
Disable RESETN. GPIO function PIO0_5 is selected on this pin. Any other movable function can be assigned to pin PIO0_5.
0x1
SWCLK
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.
2
1
read-write
ENABLED
Enable SWCLK. This function is enabled on pin PIO0_3.
0
DISABLED
Disable SWCLK. GPIO function PIO0_3 is selected on this pin. Any other movable function can be assigned to pin PIO0_3.
0x1
SWDIO
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default.
3
1
read-write
ENABLED
Enable SWDIO. This function is enabled on pin PIO0_2.
0
DISABLED
Disable SWDIO. GPIO function PIO0_2 is selected on this pin. Any other movable function can be assigned to pin PIO0_2.
0x1
VDDCMP
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.
8
1
read-write
ENABLED
Enable VDDCMP. This function is enabled on pin PIO0_6.
0
DISABLED
Disable VDDCMP. GPIO function PIO0_6 (default) or any other movable function can be assigned to pin PIO0_6.
0x1
XTALIN
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.
4
1
read-write
ENABLED
Enable XTALIN. This function is enabled on pin PIO0_8.
0
DISABLED
Disable XTALIN. GPIO function PIO0_8 (default) or any other movable function can be assigned to pin PIO0_8.
0x1
XTALOUT
Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin.
5
1
read-write
ENABLED
Enable XTALOUT. This function is enabled on pin PIO0_9.
0
DISABLED
Disable XTALOUT. GPIO function PIO0_9 (default) or any other movable function can be assigned to pin PIO0_9.
0x1
SYSCON
System configuration (SYSCON)
SYSCON
0x0
0x0
0x3FC
registers
n
BODCTRL
BOD control register
0x150
32
read-write
n
0x0
0x0
BODINTVAL
BOD interrupt level
2
2
read-write
LEVEL_1
Level 1
0x1
LEVEL_2
Level 2
0x2
LEVEL_3
Level 3
0x3
BODRSTENA
BOD reset enable
4
1
read-write
DISABLE
Disable reset function.
0
ENABLE
Enable reset function.
0x1
BODRSTLEV
BOD reset level
0
2
read-write
LEVEL_1
Level 1
0x1
LEVEL_2
Level 2
0x2
LEVEL_3
Level 3
0x3
CLKOUTDIV
PLL control
0xE8
32
read-write
n
0x0
0x0
DIV
CLKOUT clock divider values. 0: Disable CLKOUT clock divider 1: Divide by 1 to 255: Divide by 255
0
8
read-write
CLKOUTSEL
CLKOUT clock source select
0xE0
32
read-write
n
0x0
0x0
SEL
CLKOUT clock source.
0
2
read-write
IRC
IRC oscillator
0
SEL_0
IRC oscillator
0
SYSOSC
Crystal oscillator (SYSOSC)
0x1
SEL_1
Crystal oscillator (SYSOSC)
0x1
Watchdog
Watchdog oscillator
0x2
SEL_2
Watchdog oscillator
0x2
main_clk
Main clock
0x3
SEL_3
Main clock
0x3
CLKOUTUEN
CLKOUT clock source update enable
0xE4
32
read-write
n
0x0
0x0
ENA
Enable CLKOUT clock source update.
0
1
read-write
ENA_0
No change
0
ENA_1
Update clock source
0x1
DEVICE_ID
Part ID register
0x3F8
32
read-only
n
0x0
0x0
DEVICEID
Part ID
0
32
read-only
EXTTRACECMD
External trace buffer command register
0xFC
32
read-write
n
0x0
0x0
START
Trace start command. Writing a one to this bit sets the TSTART signal to the MTB to HIGH and starts tracing if the TSTARTEN bit in the MTB master register is set to one as well.
0
1
read-write
STOP
Trace stop command. Writing a one to this bit sets the TSTOP signal in the MTB to HIGH and stops tracing if the TSTOPEN bit in the MTB master register is set to one as well.
1
1
read-write
IOCONCLKDIV0
Peripheral clock 0 to the IOCON block for programmable glitch filter
0x14C
32
read-write
n
0x0
0x0
DIV
IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
IOCONCLKDIV1
Peripheral clock 1 to the IOCON block for programmable glitch filter
0x148
32
read-write
n
0x0
0x0
DIV
IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
IOCONCLKDIV2
Peripheral clock 2 to the IOCON block for programmable glitch filter
0x144
32
read-write
n
0x0
0x0
DIV
IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
IOCONCLKDIV3
Peripheral clock 3 to the IOCON block for programmable glitch filter
0x140
32
read-write
n
0x0
0x0
DIV
IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
IOCONCLKDIV4
Peripheral clock 4 to the IOCON block for programmable glitch filter
0x13C
32
read-write
n
0x0
0x0
DIV
IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
IOCONCLKDIV5
Peripheral clock 6 to the IOCON block for programmable glitch filter
0x138
32
read-write
n
0x0
0x0
DIV
IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
IOCONCLKDIV6
Peripheral clock 6 to the IOCON block for programmable glitch filter
0x134
32
read-write
n
0x0
0x0
DIV
IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
IRQLATENCY
IRQ latency register
0x170
32
read-write
n
0x0
0x0
LATENCY
8-bit latency value.
0
8
read-write
MAINCLKSEL
Main clock source select
0x70
32
read-write
n
0x0
0x0
SEL
Clock source for main clock.
0
2
read-write
IRC
IRC Oscillator.
0
SEL_0
IRC Oscillator.
0
PLL_input
PLL input.
0x1
SEL_1
PLL input.
0x1
Watchdog
Watchdog oscillator.
0x2
SEL_2
Watchdog oscillator.
0x2
PLL_output
PLL output.
0x3
SEL_3
PLL output.
0x3
MAINCLKUEN
Main clock source update enable
0x74
32
read-write
n
0x0
0x0
ENA
Enable main clock source update.
0
1
read-write
ENA_0
No change.
0
ENA_1
Update clock source.
0x1
NMISRC
NMI source selection register
0x174
32
read-write
n
0x0
0x0
IRQN
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1
0
5
read-write
NMIEN
Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.
31
1
read-write
PDAWAKECFG
Wake-up configuration register
0x234
32
read-write
n
0x0
0x0
ACMP
Analog comparator wake-up configuration
15
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
BOD_PD
BOD wake-up configuration
3
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
FLASH_PD
Flash wake-up configuration
2
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
IRCOUT_PD
IRC oscillator output wake-up configuration
0
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
IRC_PD
IRC oscillator power-down wake-up configuration
1
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
SYSOSC_PD
Crystal oscillator wake-up configuration
5
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
SYSPLL_PD
System PLL wake-up configuration
7
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
WDTOSC_PD
Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running
6
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PDRUNCFG
Power configuration register
0x238
32
read-write
n
0x0
0x0
ACMP
Analog comparator wake-up configuration
15
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
BOD_PD
BOD wake-up configuration
3
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
FLASH_PD
Flash wake-up configuration
2
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
IRCOUT_PD
IRC oscillator output wake-up configuration
0
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
IRC_PD
IRC oscillator power-down wake-up configuration
1
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
SYSOSC_PD
Crystal oscillator wake-up configuration
5
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
SYSPLL_PD
System PLL wake-up configuration
7
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
WDTOSC_PD
Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running
6
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PDSLEEPCFG
Deep-sleep configuration register
0x230
32
read-write
n
0x0
0x0
BOD_PD
BOD power-down control for Deep-sleep and Power-down mode
3
1
read-write
POWERED
powered
0
POWERED_DOWN
powered down
0x1
WDTOSC_PD
Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running.
6
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINTSEL0
Pin interrupt select registers N
0x178
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL1
Pin interrupt select registers N
0x17C
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL2
Pin interrupt select registers N
0x180
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL3
Pin interrupt select registers N
0x184
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL4
Pin interrupt select registers N
0x188
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL5
Pin interrupt select registers N
0x18C
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL6
Pin interrupt select registers N
0x190
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL7
Pin interrupt select registers N
0x194
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_28 correspond to numbers 0 to 28).
0
6
read-write
PINTSEL[0]
Pin interrupt select registers N
0x2F0
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0
6
read-write
PINTSEL[1]
Pin interrupt select registers N
0x46C
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0
6
read-write
PINTSEL[2]
Pin interrupt select registers N
0x5EC
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0
6
read-write
PINTSEL[3]
Pin interrupt select registers N
0x770
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0
6
read-write
PINTSEL[4]
Pin interrupt select registers N
0x8F8
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0
6
read-write
PINTSEL[5]
Pin interrupt select registers N
0xA84
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0
6
read-write
PINTSEL[6]
Pin interrupt select registers N
0xC14
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0
6
read-write
PINTSEL[7]
Pin interrupt select registers N
0xDA8
32
read-write
n
0x0
0x0
INTPIN
Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17).
0
6
read-write
PIOPORCAP0
POR captured PIO status 0
0x100
32
read-write
n
0x0
0x0
PIOSTAT
State of PIO0_17 through PIO0_0 at power-on reset
0
18
read-only
PRESETCTRL
Peripheral reset control register
0x4
32
read-write
n
0x0
0x0
ACMP_RST_N
Analog comparator reset control.
12
1
read-write
ACMP_RST_N_0
Assert the analog comparator reset.
0
ACMP_RST_N_1
Clear the analog comparator controller reset.
0x1
FLASH_RST_N
Flash controller reset control.
11
1
read-write
FLASH_RST_N_0
Assert the flash controller reset.
0
FLASH_RST_N_1
Clear the flash controller reset.
0x1
GPIO_RST_N
GPIO and GPIO pin interrupt reset control.
10
1
read-write
GPIO_RST_N_0
Assert the GPIO reset.
0
GPIO_RST_N_1
Clear the GPIO reset.
0x1
I2C0_RST_N
I2C0 reset control.
6
1
read-write
I2C0_RST_N_0
Assert the I2C0 reset.
0
I2C0_RST_N_1
Clear the I2C0 reset.
0x1
MRT_RST_N
Multi-rate timer (MRT) reset control.
7
1
read-write
MRT_RST_N_0
Assert the MRT reset.
0
MRT_RST_N_1
Clear the MRT reset.
0x1
SCT_RST_N
SCT reset control.
8
1
read-write
SCT_RST_N_0
Assert the SCT reset.
0
SCT_RST_N_1
Clear the SCT reset.
0x1
SPI0_RST_N
SPI0 reset control.
0
1
read-write
SPI0_RST_N_0
Assert the SPI0 reset.
0
SPI0_RST_N_1
Clear the SPI0 reset.
0x1
SPI1_RST_N
SPI1 reset control.
1
1
read-write
SPI1_RST_N_0
Assert the SPI1 reset.
0
SPI1_RST_N_1
Clear the SPI1 reset.
0x1
UART0_RST_N
USART0 reset control.
3
1
read-write
UART0_RST_N_0
Assert the USART0 reset.
0
UART0_RST_N_1
Clear the USART0 reset.
0x1
UART1_RST_N
USART1 reset control.
4
1
read-write
UART1_RST_N_0
Assert the USART1 reset.
0
UART1_RST_N_1
Clear the USART1 reset.
0x1
UART2_RST_N
USART2 reset control.
5
1
read-write
UART2_RST_N_0
Assert the USART2 reset.
0
UART2_RST_N_1
Clear the USART2 reset.
0x1
UARTFRG_RST_N
USART fractional baud rate generator(UARTFRG) reset control.
2
1
read-write
UARTFRG_RST_N_0
Assert the UARTFRG reset.
0
UARTFRG_RST_N_1
Clear the UARTFRG reset.
0x1
WKT_RST_N
Self-wake-up timer (WKT) reset control.
9
1
read-write
WKT_RST_N_0
Assert the WKT reset.
0
WKT_RST_N_1
Clear the WKT reset.
0x1
STARTERP0
Start logic 0 pin wake-up enable register 0
0x204
32
read-write
n
0x0
0x0
PINT0
GPIO pin interrupt 0 wake-up
0
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT1
GPIO pin interrupt 1 wake-up
1
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT2
GPIO pin interrupt 2 wake-up
2
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT3
GPIO pin interrupt 3 wake-up
3
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT4
GPIO pin interrupt 4 wake-up
4
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT5
GPIO pin interrupt 5 wake-up
5
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT6
GPIO pin interrupt 6 wake-up
6
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
PINT7
GPIO pin interrupt 7 wake-up
7
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
STARTERP1
Start logic 0 pin wake-up enable register 1
0x214
32
read-write
n
0x0
0x0
BOD
BOD interrupt wake-up
13
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
I2C0
I2C0 interrupt wake-up.
8
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
SPI0
SPI0 interrupt wake-up
0
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
SPI1
SPI1 interrupt wake-up
1
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
USART0
USART0 interrupt wake-up. Configure USART in synchronous slave mode.
3
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
USART1
USART1 interrupt wake-up. Configure USART in synchronous slave mode.
4
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
USART2
USART2 interrupt wake-up. Configure USART in synchronous slave mode.
5
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
WKT
Self-wake-up timer interrupt wake-up
15
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
WWDT
WWDT interrupt wake-up
12
1
read-write
DISABLED
Disabled
0
ENABLED
Enabled
0x1
SYSAHBCLKCTRL
System clock control
0x80
32
read-write
n
0x0
0x0
ACMP
Enables clock to analog comparator.
19
1
read-write
ACMP_0
Disable.
0
ACMP_1
Enable.
0x1
CRC
Enables clock for CRC.
13
1
read-write
CRC_0
Disable.
0
CRC_1
Enable.
0x1
FLASH
Enables clock for flash.
4
1
read-write
FLASH_0
Disable.
0
FLASH_1
Enable.
0x1
FLASHREG
Enables clock for flash register interface.
3
1
read-write
FLASHREG_0
Disable.
0
FLASHREG_1
Enable.
0x1
GPIO
Enables clock for GPIO port registers and GPIO pin interrupt registers.
6
1
read-write
GPIO_0
Disable.
0
GPIO_1
Enable.
0x1
I2C0
Enables clock for I2C0.
5
1
read-write
I2C0_0
Disable.
0
I2C0_1
Enable.
0x1
IOCON
Enables clock for IOCON block.
18
1
read-write
IOCON_0
Disable.
0
IOCON_1
Enable.
0x1
MRT
Enables clock for multi-rate timer.
10
1
read-write
MRT_0
Disable.
0
MRT_1
Enable.
0x1
RAM0_1
Enables clock for SRAM0 and SRAM1.
2
1
read-write
RAM0_1_0
Disable.
0
RAM0_1_1
Enable.
0x1
ROM
Enables clock for ROM.
1
1
read-write
ROM_0
Disable.
0
ROM_1
Enable.
0x1
SCT
Enables clock for state configurable timer SCTimer/PWM.
8
1
read-write
SCT_0
Disable.
0
SCT_1
Enable.
0x1
SPI0
Enables clock for SPI0.
11
1
read-write
SPI0_0
Disable.
0
SPI0_1
Enable.
0x1
SPI1
Enables clock for SPI1.
12
1
read-write
SPI1_0
Disable.
0
SPI1_1
Enable.
0x1
SWM
Enables clock for switch matrix.
7
1
read-write
SWM_0
Disable.
0
SWM_1
Enable.
0x1
SYS
Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1.
0
1
read-write
UART0
Enables clock for USART0.
14
1
read-write
UART0_0
Disable.
0
UART0_1
Enable.
0x1
UART1
Enables clock for USART1.
15
1
read-write
UART1_0
Disable.
0
UART1_1
Enable.
0x1
UART2
Enables clock for USART2.
16
1
read-write
UART2_0
Disable.
0
UART2_1
Enable.
0x1
WKT
Enables clock for self-wake-up timer.
9
1
read-write
WKT_0
Disable.
0
WKT_1
Enable.
0x1
WWDT
Enables clock for WWDT.
17
1
read-write
WWDT_0
Disable.
0
WWDT_1
Enable.
0x1
SYSAHBCLKDIV
System clock divider
0x78
32
read-write
n
0x0
0x0
DIV
System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
SYSMEMREMAP
System Remap register
0x0
32
read-write
n
0x0
0x0
MAP
System memory remap. Value 0x3 is reserved.
0
2
read-write
BOOT_LOADER_MODE
Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
0
USER_RAM_MODE
User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
0x1
USER_FLASH_MODE
User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
0x2
SYSOSCCTRL
system oscillator control
0x20
32
read-write
n
0x0
0x0
BYPASS
oscillator (Xtal) Test Mode input (Active High)
0
1
read-write
FREQRANGE
oscillator low / high transconductance selection input (Active High) 1-20MHz '0' : 15-50MHz '1'
1
1
read-write
SYSPLLCLKSEL
System PLL clock source select register
0x40
32
read-write
n
0x0
0x0
SEL
System PLL clock source
0
2
read-write
IRC
IRC
0
SYSOSC
Crystal Oscillator (SYSOSC)
0x1
CLKIN
CLKIN. External clock input.
0x3
SYSPLLCLKUEN
System PLL clock source update enable register
0x44
32
read-write
n
0x0
0x0
ENA
Enable system PLL clock source update
0
1
read-write
NO_CHANGE
no change
0
UPDATED
update clock source
0x1
SYSPLLCTRL
PLL control
0x8
32
read-write
n
0x0
0x0
MSEL
Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32
0
5
read-write
PSEL
Post divider ratio P. The division ratio is 2 x P.
5
2
read-write
PSEL_0
P = 1
0
PSEL_1
P = 2
0x1
PSEL_2
P = 4
0x2
PSEL_3
P = 8
0x3
SYSPLLSTAT
PLL status
0xC
32
read-only
n
0x0
0x0
LOCK
PLL0 lock indicator
0
1
read-only
SYSRSTSTAT
System reset status register
0x30
32
read-write
n
0x0
0x0
BOD
Status of the Brown-out detect reset.
3
1
read-write
BOD_0
No BOD reset detected.
0
BOD_1
BOD reset detected. Writing a one clears this reset.
0x1
EXTRST
Status of the external RESET pin. External reset status.
1
1
read-write
EXTRST_0
No reset event detected.
0
EXTRST_1
Reset detected. Writing a one clears this reset.
0x1
POR
POR reset status.
0
1
read-write
POR_0
No POR detected.
0
POR_1
POR detected. Writing a one clears this reset.
0x1
SYSRST
Status of the software system reset.
4
1
read-write
SYSRST_0
No System reset detected.
0
SYSRST_1
System reset detected. Writing a one clears this reset.
0x1
WDT
Status of the Watchdog reset.
2
1
read-write
WDT_0
No WDT reset detected.
0
WDT_1
WDT reset detected. Writing a one clears this reset.
0x1
SYSTCKCAL
System tick timer calibration register
0x154
32
read-write
n
0x0
0x0
CAL
System tick timer calibration value.
0
26
read-write
UARTCLKDIV
USART clock divider
0x94
32
read-write
n
0x0
0x0
DIV
USART fractional baud rate generator clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255.
0
8
read-write
UARTFRGDIV
USART1 to USART4 common fractional generator divider value
0xF0
32
read-write
n
0x0
0x0
DIV
Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set to 0xFF to use with the fractional baud rate generator.
0
8
read-write
UARTFRGMULT
USART1 to USART4 common fractional generator divider value
0xF4
32
read-write
n
0x0
0x0
MULT
Numerator of the fractional divider. MULT is equal to the programmed value.
0
8
read-write
WDTOSCCTRL
Watchdog oscillator control
0x24
32
read-write
n
0x0
0x0
DIVSEL
Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64
0
5
read-write
FREQSEL
Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz
5
4
read-write
USART0
USARTs
USART
0x0
0x0
0x28
registers
n
USART0
3
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
32
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
0
16
read-write
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
32
read-write
n
0x0
0x0
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
1
read-write
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge of SCLK.
0x1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
1
read-write
DISABLED
No flow control. The transmitter does not receive any automatic flow control signal.
0
ENABLED
Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
0x1
DATALEN
Selects the data size for the USART.
2
2
read-write
BIT_7
7 bit Data length.
0
BIT_8
8 bit Data length.
0x1
BIT_9
9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
0x2
ENABLE
USART Enable.
0
1
read-write
DISABLED
Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0
ENABLED
Enabled. The USART is enabled for operation.
0x1
LOOP
Selects data loopback mode.
15
1
read-write
NORMAL
Normal operation.
0
LOOPBACK
Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
0x1
PARITYSEL
Selects what type of parity is used by the USART.
4
2
read-write
NO_PARITY
No parity.
0
EVEN_PARITY
Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
0x3
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
1
read-write
BIT_1
1 stop bit.
0
BITS_2
2 stop bits. This setting should only be used for asynchronous communication.
0x1
SYNCEN
Selects synchronous or asynchronous operation.
11
1
read-write
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
0x1
SYNCMST
Synchronous mode Master select.
14
1
read-write
SLAVE
Slave. When synchronous mode is enabled, the USART is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART is a master.
0x1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
32
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
1
read-write
DISABLED
Disabled. The USART presents all incoming data.
0
ENABLED
Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
0x1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
1
read-write
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0
CONTINOUS_CLOCK
Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
0x1
CLRCCONRX
Clear Continuous Clock.
9
1
read-write
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
0x1
TXBRKEN
Break Enable.
1
1
read-write
NORMAL
Normal operation.
0
CONTINOUS
Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
0x1
TXDIS
Transmit Disable.
6
1
read-write
ENABLED
Not disabled. USART transmitter is not disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.
0x1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
32
write-only
n
0x0
0x0
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
1
write-only
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
1
write-only
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
1
write-only
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
1
write-only
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
1
write-only
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
1
write-only
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
write-only
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
1
write-only
TXDISINTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
1
write-only
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
1
write-only
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
n
0x0
0x0
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
1
read-write
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
1
read-write
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
1
read-write
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
1
read-write
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
1
read-write
RXNOISEEN
When 1, enables an interrupt when noise is detected.
15
1
read-write
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
read-write
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
1
read-write
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
1
read-write
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
1
read-write
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
32
read-write
n
0x0
0x0
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
1
read-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
1
read-only
FRAMERRINT
Framing Error interrupt flag.
13
1
read-only
OVERRUNINT
Overrun Error interrupt flag.
8
1
read-only
PARITYERRINT
Parity Error interrupt flag.
14
1
read-only
RXNOISEINT
Received Noise interrupt flag.
15
1
read-only
RXRDY
Receiver Ready flag.
0
1
read-only
START
This bit is set when a start is detected on the receiver input.
12
1
read-only
TXDISINT
Transmitter Disabled Interrupt flag.
6
1
read-only
TXRDY
Transmitter Ready flag.
2
1
read-only
RXDAT
Receiver Data register. Contains the last character received.
0x14
32
read-only
n
0x0
0x0
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
32
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
read-only
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
1
read-only
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXNOISE
Received Noise flag.
15
1
read-only
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
32
read-write
n
0x0
0x0
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
1
read-only
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
1
write-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.Cleared by software.
11
1
write-only
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
write-only
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
1
write-only
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
14
1
write-only
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
1
read-only
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
1
read-only
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
1
write-only
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
read-only
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
1
write-only
TXDISSTAT
Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
6
1
read-only
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
1
read-only
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
1
read-only
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
32
read-write
n
0x0
0x0
TXDAT
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
read-write
USART1
USARTs
USART
0x0
0x0
0x28
registers
n
USART1
4
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
32
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
0
16
read-write
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
32
read-write
n
0x0
0x0
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
1
read-write
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge of SCLK.
0x1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
1
read-write
DISABLED
No flow control. The transmitter does not receive any automatic flow control signal.
0
ENABLED
Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
0x1
DATALEN
Selects the data size for the USART.
2
2
read-write
BIT_7
7 bit Data length.
0
BIT_8
8 bit Data length.
0x1
BIT_9
9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
0x2
ENABLE
USART Enable.
0
1
read-write
DISABLED
Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0
ENABLED
Enabled. The USART is enabled for operation.
0x1
LOOP
Selects data loopback mode.
15
1
read-write
NORMAL
Normal operation.
0
LOOPBACK
Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
0x1
PARITYSEL
Selects what type of parity is used by the USART.
4
2
read-write
NO_PARITY
No parity.
0
EVEN_PARITY
Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
0x3
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
1
read-write
BIT_1
1 stop bit.
0
BITS_2
2 stop bits. This setting should only be used for asynchronous communication.
0x1
SYNCEN
Selects synchronous or asynchronous operation.
11
1
read-write
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
0x1
SYNCMST
Synchronous mode Master select.
14
1
read-write
SLAVE
Slave. When synchronous mode is enabled, the USART is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART is a master.
0x1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
32
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
1
read-write
DISABLED
Disabled. The USART presents all incoming data.
0
ENABLED
Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
0x1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
1
read-write
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0
CONTINOUS_CLOCK
Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
0x1
CLRCCONRX
Clear Continuous Clock.
9
1
read-write
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
0x1
TXBRKEN
Break Enable.
1
1
read-write
NORMAL
Normal operation.
0
CONTINOUS
Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
0x1
TXDIS
Transmit Disable.
6
1
read-write
ENABLED
Not disabled. USART transmitter is not disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.
0x1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
32
write-only
n
0x0
0x0
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
1
write-only
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
1
write-only
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
1
write-only
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
1
write-only
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
1
write-only
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
1
write-only
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
write-only
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
1
write-only
TXDISINTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
1
write-only
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
1
write-only
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
n
0x0
0x0
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
1
read-write
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
1
read-write
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
1
read-write
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
1
read-write
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
1
read-write
RXNOISEEN
When 1, enables an interrupt when noise is detected.
15
1
read-write
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
read-write
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
1
read-write
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
1
read-write
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
1
read-write
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
32
read-write
n
0x0
0x0
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
1
read-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
1
read-only
FRAMERRINT
Framing Error interrupt flag.
13
1
read-only
OVERRUNINT
Overrun Error interrupt flag.
8
1
read-only
PARITYERRINT
Parity Error interrupt flag.
14
1
read-only
RXNOISEINT
Received Noise interrupt flag.
15
1
read-only
RXRDY
Receiver Ready flag.
0
1
read-only
START
This bit is set when a start is detected on the receiver input.
12
1
read-only
TXDISINT
Transmitter Disabled Interrupt flag.
6
1
read-only
TXRDY
Transmitter Ready flag.
2
1
read-only
RXDAT
Receiver Data register. Contains the last character received.
0x14
32
read-only
n
0x0
0x0
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
32
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
read-only
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
1
read-only
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXNOISE
Received Noise flag.
15
1
read-only
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
32
read-write
n
0x0
0x0
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
1
read-only
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
1
write-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.Cleared by software.
11
1
write-only
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
write-only
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
1
write-only
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
14
1
write-only
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
1
read-only
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
1
read-only
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
1
write-only
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
read-only
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
1
write-only
TXDISSTAT
Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
6
1
read-only
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
1
read-only
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
1
read-only
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
32
read-write
n
0x0
0x0
TXDAT
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
read-write
USART2
USARTs
USART
0x0
0x0
0x28
registers
n
USART2
5
BRG
Baud Rate Generator register. 16-bit integer baud rate divisor value.
0x20
32
read-write
n
0x0
0x0
BRGVAL
This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
0
16
read-write
CFG
USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
0x0
32
read-write
n
0x0
0x0
CLKPOL
Selects the clock polarity and sampling edge of received data in synchronous mode.
12
1
read-write
FALLING_EDGE
Falling edge. Un_RXD is sampled on the falling edge of SCLK.
0
RISING_EDGE
Rising edge. Un_RXD is sampled on the rising edge of SCLK.
0x1
CTSEN
CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.
9
1
read-write
DISABLED
No flow control. The transmitter does not receive any automatic flow control signal.
0
ENABLED
Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
0x1
DATALEN
Selects the data size for the USART.
2
2
read-write
BIT_7
7 bit Data length.
0
BIT_8
8 bit Data length.
0x1
BIT_9
9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
0x2
ENABLE
USART Enable.
0
1
read-write
DISABLED
Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.
0
ENABLED
Enabled. The USART is enabled for operation.
0x1
LOOP
Selects data loopback mode.
15
1
read-write
NORMAL
Normal operation.
0
LOOPBACK
Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
0x1
PARITYSEL
Selects what type of parity is used by the USART.
4
2
read-write
NO_PARITY
No parity.
0
EVEN_PARITY
Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.
0x2
ODD_PARITY
Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.
0x3
STOPLEN
Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
6
1
read-write
BIT_1
1 stop bit.
0
BITS_2
2 stop bits. This setting should only be used for asynchronous communication.
0x1
SYNCEN
Selects synchronous or asynchronous operation.
11
1
read-write
ASYNCHRONOUS_MODE
Asynchronous mode.
0
SYNCHRONOUS_MODE
Synchronous mode.
0x1
SYNCMST
Synchronous mode Master select.
14
1
read-write
SLAVE
Slave. When synchronous mode is enabled, the USART is a slave.
0
MASTER
Master. When synchronous mode is enabled, the USART is a master.
0x1
CTL
USART Control register. USART control settings that are more likely to change during operation.
0x4
32
read-write
n
0x0
0x0
ADDRDET
Enable address detect mode.
2
1
read-write
DISABLED
Disabled. The USART presents all incoming data.
0
ENABLED
Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.
0x1
CC
Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
8
1
read-write
CLOCK_ON_CHARACTER
Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.
0
CONTINOUS_CLOCK
Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).
0x1
CLRCCONRX
Clear Continuous Clock.
9
1
read-write
NO_EFFECT
No effect. No effect on the CC bit.
0
AUTO_CLEAR
Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
0x1
TXBRKEN
Break Enable.
1
1
read-write
NORMAL
Normal operation.
0
CONTINOUS
Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
0x1
TXDIS
Transmit Disable.
6
1
read-write
ENABLED
Not disabled. USART transmitter is not disabled.
0
DISABLED
Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.
0x1
INTENCLR
Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
0x10
32
write-only
n
0x0
0x0
DELTACTSCLR
Writing 1 clears the corresponding bit in the INTENSET register.
5
1
write-only
DELTARXBRKCLR
Writing 1 clears the corresponding bit in the INTENSET register.
11
1
write-only
FRAMERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
13
1
write-only
OVERRUNCLR
Writing 1 clears the corresponding bit in the INTENSET register.
8
1
write-only
PARITYERRCLR
Writing 1 clears the corresponding bit in the INTENSET register.
14
1
write-only
RXNOISECLR
Writing 1 clears the corresponding bit in the INTENSET register.
15
1
write-only
RXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
0
1
write-only
STARTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
12
1
write-only
TXDISINTCLR
Writing 1 clears the corresponding bit in the INTENSET register.
6
1
write-only
TXRDYCLR
Writing 1 clears the corresponding bit in the INTENSET register.
2
1
write-only
INTENSET
Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
0xC
32
read-write
n
0x0
0x0
DELTACTSEN
When 1, enables an interrupt when there is a change in the state of the CTS input.
5
1
read-write
DELTARXBRKEN
When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
11
1
read-write
FRAMERREN
When 1, enables an interrupt when a framing error has been detected.
13
1
read-write
OVERRUNEN
When 1, enables an interrupt when an overrun error occurred.
8
1
read-write
PARITYERREN
When 1, enables an interrupt when a parity error has been detected.
14
1
read-write
RXNOISEEN
When 1, enables an interrupt when noise is detected.
15
1
read-write
RXRDYEN
When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
0
1
read-write
STARTEN
When 1, enables an interrupt when a received start bit has been detected.
12
1
read-write
TXDISEN
When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
6
1
read-write
TXRDYEN
When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
2
1
read-write
INTSTAT
Interrupt status register. Reflects interrupts that are currently enabled.
0x24
32
read-write
n
0x0
0x0
DELTACTS
This bit is set when a change in the state of the CTS input is detected.
5
1
read-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.
11
1
read-only
FRAMERRINT
Framing Error interrupt flag.
13
1
read-only
OVERRUNINT
Overrun Error interrupt flag.
8
1
read-only
PARITYERRINT
Parity Error interrupt flag.
14
1
read-only
RXNOISEINT
Received Noise interrupt flag.
15
1
read-only
RXRDY
Receiver Ready flag.
0
1
read-only
START
This bit is set when a start is detected on the receiver input.
12
1
read-only
TXDISINT
Transmitter Disabled Interrupt flag.
6
1
read-only
TXRDY
Transmitter Ready flag.
2
1
read-only
RXDAT
Receiver Data register. Contains the last character received.
0x14
32
read-only
n
0x0
0x0
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXDATSTAT
Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
0x18
32
read-only
n
0x0
0x0
FRAMERR
Framing Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
read-only
PARITYERR
Parity Error status flag. This bit is valid when there is a character to be read in the RXDAT register and reflects the status of that character. This bit will be set when a parity error is detected in a received character.
14
1
read-only
RXDAT
The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings.
0
9
read-only
RXNOISE
Received Noise flag.
15
1
read-only
STAT
USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
0x8
32
read-write
n
0x0
0x0
CTS
This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled.
4
1
read-only
DELTACTS
This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
5
1
write-only
DELTARXBRK
This bit is set when a change in the state of receiver break detection occurs.Cleared by software.
11
1
write-only
FRAMERRINT
Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source.
13
1
write-only
OVERRUNINT
Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost.
8
1
write-only
PARITYERRINT
Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
14
1
write-only
RXBRK
Received Break. This bit reflects the current state of the receiver break detection logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high.
10
1
read-only
RXIDLE
Receiver Idle. When 0, indicates that the receiver is currently in the process of receiving data. When 1, indicates that the receiver is not currently in the process of receiving data.
1
1
read-only
RXNOISEINT
Received Noise interrupt flag. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. This flag is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception.
15
1
write-only
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers.
0
1
read-only
START
This bit is set when a start is detected on the receiver input. Its purpose is primarily to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. Cleared by software.
12
1
write-only
TXDISSTAT
Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1).
6
1
read-only
TXIDLE
Transmitter Idle. When 0, indicates that the transmitter is currently in the process of sending data.When 1, indicate that the transmitter is not currently in the process of sending data.
3
1
read-only
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift register.
2
1
read-only
TXDAT
Transmit Data register. Data to be transmitted is written here.
0x1C
32
read-write
n
0x0
0x0
TXDAT
Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available and any conditions for transmitting data are met: CTS low (if CTSEN bit = 1), TXDIS bit = 0.
0
9
read-write
WKT
Wake Up Timer(WKT)
WKT
0x0
0x0
0x10
registers
n
WKT
15
COUNT
Counter register.
0xC
32
read-write
n
0x0
0x0
VALUE
A write to this register pre-loads start count value into the timer and starts the count-down sequence. A read reflects the current value of the timer.
0
32
read-write
CTRL
Self wake-up timer control register.
0x0
32
read-write
n
0x0
0x0
ALARMFLAG
Wake-up or alarm timer flag.
1
1
read-write
NO_TIME_OUT
No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect.
0
TIME_OUT
Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power-down if the clock source is the low power oscillator. Writing a 1 clears this status bit.
0x1
CLEARCTR
Clears the self wake-up timer.
2
1
read-write
NO_EFFECT
No effect. Reading this bit always returns 0.
0
CLEAR_THE_COUNTER
Clear the counter. Counting is halted until a new count value is loaded.
0x1
CLKSEL
Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set.
0
1
read-write
DIVIDED_IRC_CLOCK
Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 us increments. Remark: This clock is not available in not available in Deep-sleep, power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these modes.
0
LOW_POWER_CLOCK
This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 us increments. The accuracy of this clock is limited to +/- 40 % over temperature and processing. Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed.
0x1
WWDT
Windowed Watchdog Timer (WWDT)
WWDT
0x0
0x0
0x1C
registers
n
WDT
12
FEED
Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC.
0x8
32
write-only
n
0x0
0x0
FEED
Feed value should be 0xAA followed by 0x55.
0
8
write-only
MOD
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
0x0
32
read-write
n
0x0
0x0
LOCK
Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset.
5
1
read-write
WDEN
Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.
0
1
read-write
STOP
Stop. The watchdog timer is stopped.
0
RUN
Run. The watchdog timer is running.
0x1
WDINT
Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.
3
1
read-write
WDPROTECT
Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
4
1
read-write
FLEXIBLE
Flexible. The watchdog time-out value (TC) can be changed at any time.
0
THRESHOLD
Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
0x1
WDRESET
Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
1
1
read-write
INTERRUPT
Interrupt. A watchdog time-out will not cause a chip reset.
0
RESET
Reset. A watchdog time-out will cause a chip reset.
0x1
WDTOF
Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1.
2
1
read-write
TC
Watchdog timer constant register. This 24-bit register determines the time-out value.
0x4
32
read-write
n
0x0
0x0
COUNT
Watchdog time-out value.
0
24
read-write
TV
Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer.
0xC
32
read-only
n
0x0
0x0
COUNT
Counter timer value.
0
24
read-only
WARNINT
Watchdog Warning Interrupt compare value.
0x14
32
read-write
n
0x0
0x0
WARNINT
Watchdog warning interrupt compare value.
0
10
read-write
WINDOW
Watchdog Window compare value.
0x18
32
read-write
n
0x0
0x0
WINDOW
Watchdog window value.
0
24
read-write